Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status
Reexamination Certificate
2007-09-25
2007-09-25
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Processor status
C710S260000, C718S102000
Reexamination Certificate
active
11117881
ABSTRACT:
A method and system for maintaining a desired service level for a processor receiving excessive interrupts. The method includes the operation of defining an interrupt processing period during which interrupts will be measured for a processor. The amounts of time spent by the processor during the interrupt processing period in interrupt context can be measured. Another operation is detecting an interrupt storm occurring for the processor based on the amounts of time spent by the processor in interrupt context. The interrupts received by the processor can then be restricted for a period of the processor's total processing time when an interrupt storm has been detected.
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Van Jacobson, et al., Congestion Avoidance and Control, Nov. 1988, pp. 1-25.
Hoemann Jerry A.
Wright Randall F.
Auve Glenn A.
Hewlett--Packard Development Company, L.P.
Vu Trisha
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