Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-29
2009-11-17
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07620918
ABSTRACT:
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
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Khoo Kei-Yong
Lai Yung-Te
Lin Chih-Chang
Pandey Manish
Siarowski Bret
Cadence Design Systems Inc.
Chiang Jack
Tat Binh C
Vista IP Law Group LLP
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