Method and system for logic equivalence checking

Details Method and system for logic equivalence checking Method and system for logic equivalence checking

2007-08-29

2009-11-17

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07620919

ABSTRACT:
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

REFERENCES:
patent: 5754454 (1998-05-01), Pixley et al.
patent: 6301687 (2001-10-01), Jain et al.
patent: 6408424 (2002-06-01), Mukherjee et al.
patent: 6449750 (2002-09-01), Tsuchiya
patent: 6457162 (2002-09-01), Stanion
patent: 6473884 (2002-10-01), Ganai et al.
patent: 6742174 (2004-05-01), Chen et al.
patent: 6931611 (2005-08-01), Martin et al.
patent: 6993730 (2006-01-01), Higgins et al.
Beatty, D.L. et al. “Fast Incremental Circuit Analysis Using Extracted Hierarchy” Proceedings of the 25th ACM/IEEE Conference on Design Automation, Atlantic City, NJ, 1988, pp. 495-500.
Burch, J.R. et al. “Tight Integration of Combinational Verification Methods” Proceedings of the 1998 International Conference on Computer-Aided Design (ICCAD 98), San Jose, CA, 1998, pp. 570-576.
Ebeling, C. et al. “Validating VLSI Circuit Layout by Wirelist Comparison” Proceedings of the International Conference on Computer-Aided Design (ICCAD 83), Santa Clara, CA, Sep. 12-15, 1983, pp. 172-173.
Fielding, R. et al., “Hypertext Transfer Protocol—Http/1.1”, Jun. 1998, located at www.ietf.org/rfc/rfc2616.txt.
Gupta, A. “Formal Hardware Verification Methods: A Survey” Formal Methods in System Design, 1992, vol. 1., pp. 151-238.
Kato, K. “Persistent Caching: An Implementation Technique for Complex Objects with Object Identity” IEEE Transactions on Software Engineering, Jul. 1992, vol. 18, No. 7, pp. 631- 645.
Kuehlmann, A. et al. “Equivalence Checking Using Cuts and Heaps” Proceedings of 34th Annual Design Automation Conference (DAC 97) , Anaheim, CA, Jun. 1997, pp. 263-268.
Kunz, W. “Hannibal: An Efficient Tool for Logic Verification Based on Recursive Learning” Proceedings of 1993 International Conference on Computer-Aided Design (ICCAD 93), Santa Clara, CA, Nov. 1993, pp. 538-543.
Liskov, B. et al. “Providing Persistent Objects in Distributed Systems” Proceedings of the 13th European Conference on Object-Oriented Programming (ECOOP 99) Jun. 1999, 28 pages.
Moskewicz, M. “CHAFF: Engineering an Efficient SAT Solver” Proceedings of the 38th Design Automation Conference (DAC 01), Las Vegas, NV, Jun. 2001, 6 pages.
Smith, B. et al. “Exploiting Result Equivalence in Caching Dynamic Web Content” , The 2nd USENIX Symposium on Internet Technologies and Systems (USITS 99), Boulder, CO, Oct. 11-14, 1999, 12 pages.
Non-Final Office Action dated Jan. 12, 2009 for U.S. Appl. No. 11/847,177.

Affiliated with

Also associated with

Rating

Method and system for logic equivalence checking does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for logic equivalence checking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for logic equivalence checking will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4102659