Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-12-11
2000-08-22
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 35, 714768, G06F 1202
Patent
active
061087971
ABSTRACT:
When loading executable machine code into memories, the defective memory locations can be bypassed by properly inserting jump instructions or dummy memory allocation instructions in the program code. Prior to loading the executable code into the memories, defective memory locations are checked and recorded first. The source program code are analyzed to see which instruction step will fall into defective memory locations. Dummy memory space allocation instructions or additional jump instructions, are inserted in the original micro code, such that defective memory locations can be bypassed when the modified program code is loaded into the working memory space. The present invention is useful for loading executable programs in programmable and verifiable memories, such as Flash/EEPROM, EPROM, SRAM and DRAM, etc.
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Lin Shi-Tron
Wu Meng-Tsang
Yang Ding-Yuan
Beausoliel, Jr. Robert W.
Revak Christopher
Winbond Electronics Corp.
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