Method and system for layout and schematic generation for hetero

Details Method and system for layout and schematic generation for hetero Method and system for layout and schematic generation for hetero

1997-11-12

1999-06-08

Tokar, Michael J.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 38, H03K 19177, H03K 738

Patent

active

059107332

ABSTRACT:
A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.

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