Method and system for latching an address for accessing synchron

Details Method and system for latching an address for accessing synchron Method and system for latching an address for accessing synchron

1997-11-12

2000-03-28

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711 3, 711167, 36523008, G06F 1200, G11C 11413

Patent

active

060444320

ABSTRACT:
A method and system for latching an address for accessing a synchronous static random access memory (SRAM). A first address status signal of the SRAM is driven active, triggering an SRAM to latch the address on an address bus coupled therewith. A second address status signal is received when a valid address is placed on the address bus. In response, the first address status signal is driven inactive. This forces the last address latched by the SRAM to be the one indicated by the second address status signal. Then, a determination is made as to whether SRAM access is required based on the address placed on the bus. SRAM access may not be required if the current cycle is either non-cacheable or a miss in the SRAM. When SRAM access is not required, the first address status signal is driven active. In the alternative, when SRAM access is required, the first address status signal is maintained inactive. The first address status signal is maintained inactive until the SRAM is ready to accept a second address.

REFERENCES:
patent: 5497355 (1996-03-01), Mills et al.
patent: 5604884 (1997-02-01), Thome et al.
patent: 5634030 (1997-05-01), Nakano
patent: 5801996 (1998-09-01), Seyyedy et al.

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