Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-12-13
2010-11-30
Chery, Mardochee (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711SE12069, C711S134000, C711S135000, C711S136000
Reexamination Certificate
active
07844779
ABSTRACT:
Determining and applying a cache replacement policy for a computer application running in a computer processing system is accomplished by receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache, allocating a tag table for each processor core, where the tag table keeps track of an index of processor core miss rates, and setting a threshold to define a level of cache usefulness, depending on whether or not the index of processor core miss rates exceeds the threshold. Checking the threshold and when the threshold is not exceeded, then a shared cache standard policy for cache replacement is applied. When the threshold is exceeded, then the cache line from the processor core running the application is evicted from the shared cache.
REFERENCES:
patent: 6681297 (2004-01-01), Chauvel et al.
patent: 6978349 (2005-12-01), Wilkes
patent: 7039760 (2006-05-01), Arimilli et al.
patent: 2002/0073282 (2002-06-01), Chauvel et al.
patent: 2004/0098541 (2004-05-01), Megiddo et al.
patent: 2005/0071564 (2005-03-01), Luick
patent: 2006/0053257 (2006-03-01), Sistla et al.
patent: 2006/0143390 (2006-06-01), Kottapalli
patent: 2006/0179196 (2006-08-01), Gray
patent: 2006/0218352 (2006-09-01), Shannon et al.
patent: 2007/0079072 (2007-04-01), Collier et al.
patent: 2008/0086600 (2008-04-01), Qiao
patent: 2009/0193196 (2009-07-01), Kornegay et al.
patent: 2009/0300631 (2009-12-01), Karlapalem et al.
A Dynamically Reconfigurable Cache for Multithreaded Processors, Settle et al., pp. 1-35.
Cooperative Caching for Chip Multiprocessors, Chang et al., Proceedings of the 33rd International Symposium on Computer Architecture (ISCA'06), 2006 IEEE.
Thread-Shared Software Code Caches, Bruening eet al., Proceedings of the International Symposium on Code Generation and Optimization (CGO'06), 2006 IEEE .
Modeling Cache Sharing on Chip Multiprocessor Architectures, [online]; [retrieved on Jun. 23, 2007]; retrieved from the Internet http://216.239.51.104/search?q=cache:gu-P-tfuXoAJ:www.cs.wisc.edu/-... multiprocessor+architectures&hL=en&ct=clnk&cd=1&gl=us&client=safari.
Kornegay Marcus L.
Pham Ngan N.
Cantor & Colburn LLP
Chery Mardochee
International Business Machines - Corporation
Rossiter Sean
Seal Cynthia
LandOfFree
Method and system for intelligent and dynamic cache... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for intelligent and dynamic cache..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for intelligent and dynamic cache... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4243777