Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-13
2004-09-07
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S019000
Reexamination Certificate
active
06789242
ABSTRACT:
BACKGROUND
1. Field
The invention relates to software tools for assisting circuit designers in the task of analyzing integrated circuit designs.
2. Description of the Related Art
A circuit design must be carefully designed and tested before it is implemented as an integrated circuit on a silicon chip. If a circuit design has faults that make it operate incorrectly after implementation, the effort and expense of implementing the faulty circuit is wasted. In addition, significant effort and expense is involved in finding and correcting the faults. The need for accurate designs have become increasingly important as integrated circuits have become larger and more complex. Numerous software tools are available for designing and analyzing integrated circuit designs. An aspect of certain software design tools is a user interface that allows a designer to view a gate-level representation of a circuit.
FIG. 1
depicts an exemplary gate level design of a circuit
100
that has storage elements and combinatorial elements. The storage elements can be a delay-type flip-flop such as, by way of example, D flip-flops
102
-
107
. The combinatorial gates include inverters
108
,
109
, and
110
, AND gates
111
and
112
, NOR gate
113
, and OR gate
114
. Each of the flip-flops
102
-
107
outputs the signal on a line coupled to its respective D input when it receives an appropriate clock signal on its CLK input. The combinatorial gates, on the other hand, produce an output based on the value of their input signals almost instantaneously in response to a change in the signal value carried on their input lines.
Software tools exist for simulating the behavior of circuit
100
. If circuit
100
does not behave as expected, the designer must determine where the fault is. For example, the designer may have designed circuit
100
to produce a signal value of “1” on an output line
122
given a signal value of “0” on an input line
120
. Thus, as depicted in
FIG. 1
, the signal value of “0” carried on output line
122
is not expected and thus, signifies an error in circuit
100
. The designer typically diagnoses the circuit using conventional simulation or verification tools. A significant disadvantage of existing tools is that the tools only show signal values carried on the input and output lines at a single time-frame. This is shown in
FIG. 1
as “1s” and “0s” at the various signal lines. The signal values depicted in
FIG. 1
are a snapshot of the signal values carried on the signal lines in circuit
100
at a particular point in time.
FIG. 2
depicts an exemplary user interface display of a conventional software tool depicting signal values for a circuit at a single point in time (in this case, time =3400 nano seconds (ns)). The information displayed in
FIG. 2
is of limited use in diagnosing sequential circuits that include storage elements, such as circuit
100
. While the value of a combinatorial gate can be derived from the values of its inputs, the output values of a storage element depend upon the signal value of its input at a previous time-frame. A drawback of the existing software tools is that they fail to display signal values at the required time-frames to facilitate efficient design diagnosis.
For example, consider the situation in which the signal value carried on the line coupled to the output of AND gate
112
is incorrect, causing the signal transmitted at the output of flip-flop
107
(once clocked) to be incorrect. A snapshot showing the values of the various signal lines after flip-flop
107
is clocked would show the incorrect value carried on output line
122
(the output of flip-flop
107
), but the previous time-frame's input and output signal values, including those for combinatorial elements
110
,
112
, and
114
would no longer be shown. Therefore, the origin or cause of the incorrect value would not be obvious. Thus, conventional software tools are inadequate for facilitating diagnosis of sequential logic designs.
SUMMARY
The present disclosure is directed to a system and corresponding methods for providing a meaningful signal value display between input signals and output signals of storage elements in a circuit design. One aspect of the present invention is a software verification tool that facilitates circuit design diagnosis by providing a multiple time-frame signal value display across the components in a circuit design, including storage elements.
For purposes of summarizing the invention, certain aspects, advantages, and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any one particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.
In one embodiment, a method for displaying a schematic diagram of a circuit showing multiple time-frame signal values across storage elements includes: identifying one or more time-frames in a circuit, the one or more time-frames being determined by a number of consecutive storage elements in a signal path in the circuit; receiving a request to display signal values associated with a first storage element at a time-frame t; displaying a first signal value carried on a first signal line coupled to an output of the first storage element, the first signal value being at time-frame t; and displaying a second signal value carried on a second signal line coupled to an input of the first storage element, the second signal value being at time-frame t−1.
In another embodiment, a method for displaying signal values at multiple time-frames includes: identifying one or more storage elements in a signal path in a circuit, each of the one or more storage elements identifying a new time-frame; displaying a first signal value carried on a first signal line coupled to one output of a first storage element at a first time-frame; and displaying a second signal value carried on a second signal line coupled to an input of the first storage element at a second time-frame.
In still another embodiment, a computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to: identify one or more time-frames in a circuit, the one or more time-frames being determined by a number of consecutive storage elements in a signal path in the circuit; receive a request to display signal values associated with a first storage element at a time-frame t; display a first signal value carried on a first signal line coupled to an output of the first storage element, the first signal value being at time-frame t; and display a second signal value carried on a second signal line coupled to an input of the first storage element, the second signal value being at time-frame t−1.
In yet another embodiment, a computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to: identify one or more storage elements in a signal path in a circuit, each of the one or more storage elements identifying a new time-frame; display a first signal value carried on a first signal line coupled to one output of a first storage element at a first time-frame; and display a second signal value carried on a second signal line coupled to an input of the first storage element at a second time-frame.
In one embodiment, a method for displaying a schematic diagram of a circuit showing multiple time-frame signal values across storage elements includes: identifying a loop in a signal path, the loop having: a first element at a first time-frame, a second element at a second time-frame, a first signal line coupled to an output of the first element and an input of the second element, and a second signal line coupled to an output of the second element and an input of the first element; replicating the first element at a third time-frame; c
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Garbowski Leigh M.
LandOfFree
Method and system for integrated circuit design and diagnosis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for integrated circuit design and diagnosis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for integrated circuit design and diagnosis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3274220