Method and system for inplace symbolic simulation over...

Details Method and system for inplace symbolic simulation over... Method and system for inplace symbolic simulation over...

2007-10-16

2007-10-16

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S014000

Reexamination Certificate

active

11084778

ABSTRACT:
A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.

REFERENCES:
patent: 6557151 (2003-04-01), Donath et al.
patent: 2004/0049371 (2004-03-01), Fraer et al.
patent: 2005/0268265 (2005-12-01), Ly et al.

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