Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2000-04-04
2004-11-16
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C711S161000
Reexamination Certificate
active
06820224
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to embedded memory devices, and more particularly to increasing the yield of embedded memory devices.
BACKGROUND OF THE INVENTION
As central processing units for computer systems have undergone constant improvement, computer systems have continued to increase the number of bits they support and their processing speeds. Matching the improvement in other computer system components can be difficult. Included in these components is a semiconductor memory component, such as random access memory (RAM) for the computer system.
Usual attempts to improve the RAM of a computer system involve increases in the amount of RAM in the system. Developers attempt to provide a maximum amount of RAM with minimum area consumption. The decrease in transistor size has allowed greater capacity in RAM circuits. However, area does increase, which causes the percentage of natural good die per wafer to decrease. Thus, the ability to compensate for defective portions of a die becomes more important.
Memory chips typically employ redundancy to supply spare rows/columns of memory cells on the die. The redundant row/columns suitably aid in maintaining higher capacity and compensate for processing defects in the die by replacing defective rows/columns. In order to implement the use of the redundant row/columns, the chip is usually programmed with fuses to select the redundant row/column in place of the defective row/column. However, even the redundant row/columns may be defective.
Embedded memory devices are particularly concerned with maintaining a high yield of usable memory cells/bits. Embedded memory devices are complex semiconductor circuits that contain both a significant amount of memory and logic cells. After memory repair, if the embedded memory device still exhibits bit locations that are stuck at a one or zero level, the entire embedded memory device becomes unusable. A re-mapping of the failed memory bits is sometimes employed, which consolidates the usable memory cells into one continuous memory space. While re-mapping does allow use of the embedded memory device, the usable memory size is reduced, with one entire row or column discarded for only one failed memory bit.
Accordingly, a need exists for a technique of increasing yield in embedded memory devices.
SUMMARY OF THE INVENTION
The present invention meets this need and provides aspects for increasing yield in an embedded memory device. With the aspects of the present invention, a cache is provided for a memory unit of an embedded memory device. Attempts to access a failed bit memory location in the memory unit are determined. When a failed memory bit location is being accessed, substitution of a memory location in the cache for the failed bit memory location occurs.
With the present invention, an efficient approach to increasing embedded memory device yield is provided. The provision of a cache to substitute for failed memory locations in a memory portion of the embedded memory device allows utilization of memory space substantially equivalent to the intended size of the memory portion. In this manner, the number of usable memory bit locations or yield of the memory portion is increased over prior art approaches of memory re-mapping. Further, the ability to maintain utilization of an embedded memory device with failed bit locations increases production yield, since fewer devices would need to be discarded. These and other advantages of the present invention will be more fully understood in a conjunction with the following detailed description and accompanying drawings.
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patent: 5838893 (1998-11-01), Douceur
patent: 6408401 (2002-06-01), Bhavsar et al.
R. Torrance et al., “A 33 GB/s 13.4Mb Integrated Graphics Accelerator and Frame Buffer,” IEEE International Solid-State Circuits Conference1998;Digest of Technical Papers. 1998 IEEE International , 1998 pp. 340,341,461.
Chen Douglas
Lin Hung-Mao
Lin Jyh-Cherng
Dooley Matthew C.
Lamarre Guy J.
ProMOS Technologies Inc.
Sawyer Law Group LLP
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