Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-10-24
1998-08-11
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711103, 326 39, 34082583, 36471603, 36518533, 36518908, 395598, 395821, G06F 1338, H03K 19177
Patent
active
057940339
ABSTRACT:
The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.
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patent: 4879688 (1989-11-01), Turner et al.
patent: 5148527 (1992-09-01), Basso et al.
patent: 5426378 (1995-06-01), Ong
patent: 5426379 (1995-06-01), Trimberger
patent: 5670897 (1997-09-01), Kean
patent: 5705938 (1998-01-01), Kean
Aldebert Jeane-Paul
Basso Claude
Calvignac Jean
Chemla Paul
Orsatti Daniel
Chan Eddie P.
International Business Machines - Corporation
Kim Hong
Ray-Yarletts Jeanine S.
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