Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2000-11-08
2003-04-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C365S165000
Reexamination Certificate
active
06549450
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a method and system for improving the performance of silicon-on-insulator (SOI) memory arrays in an static random access memory (SRAM) architecture system.
BACKGROUND OF THE INVENTION
Each memory cell in a static random access memory (SRAM) chip is a buffer or flip-flop, and data is retained as long as power is maintained to the chip. SRAMs are realized with a bipolar technology, such as TTL, ECL, or I
2
L or with MOS technology, such as NMOS or CMOS. Bipolar SRAMs are relatively fast, having access times of 2 to 100 nsec. Power dissipation is also high, typically, 0.1 to 1.0 mW/bit. By contrast, MOS RAM access time is typically 100 nsec and power dissipation is 25 &mgr;W/bit. The combination of high circuit density, low power dissipation, and reasonable access time has led to the dominance of MOS technology in the manufacture of RAM. Hence, SRAMs having high-speed buffers are widely used in devices and equipment necessitating high-speed and high performance, such as microprocessors, communication networks, facsimile machines, modems, etc.
The performance of SRAM chips has also been significantly enhanced by the use of partially depleted silicon-on-insulator (SOI), i.e., PD-SOI, wafers in the fabrication thereof SOI wafers include an electrically insulating oxide film bonded to the active layer. It has been demonstrated that the use of PD-SOI substrate in the fabrication of an SRAM chip results in a 20-30% performance enhancement of the SRAM chip. This performance enhancement is attributed to the lowering of device junction capacitance and dynamic threshold voltage due to raised body potential. Accordingly, PD-SOI circuits have a better current drive and a higher transconductance than non-SOI circuits which leads to the performance enhancement.
Furthermore, circuits fabricated on PD-SOI have become more and more popular than circuits fabricated on a fully depleted SOI substrate. This is because the threshold voltage of devices fabricated on PD-SOI is easier to control than devices fabricated on a fully depleted SOI. Hence, devices fabricated on PD-SOI have a better short channel effect and require less quality control procedures during manufacturing.
A PD-SOI MOS device is illustrated by FIG.
1
A and designated generally by reference numeral
10
. A circuit diagram of the PD-SOI MOS device
10
is illustrated by FIG.
1
B. The device
10
is completely isolated by shallow trench
20
on both sides, and buried oxide layer
30
at the bottom. Body region
50
of the PD-SOI MOS device
10
is underneath the source
40
, channel
60
, and drain
70
regions.
Due to the existence of the body region
50
, it appears that the PD-SOI MOS device
10
is connected in parallel with a lateral parasitic bipolar device
80
underneath. As illustrated by
FIG. 1B
, the body
50
and source
40
regions form the base-emitter junction of the bipolar, while the body
50
and drain
70
regions forms the base-collector junction.
Since the body region
50
of the PD-SOI MOS device
10
is not tied to any voltage level, i.e., commonly described as being “left floating”, it is known to cause some circuit behavior problems under certain circumstances. For example, when the source
40
and drain
70
regions of the PD-SOI MOS device
10
are both stressed at a high voltage, e.g., a voltage greater than 1.8 volts, after a few milli-seconds, the p-type body region
50
of the PD-SOI device
10
is also charged up to about the same voltage level. When the source region
40
of the device
10
is suddenly dropped to ground, the forward-biased body-source junction (or base-emitter junction) will turn on the parasitic bipolar device
80
underneath the body region
50
and cause an unexpected parasitic bipolar leakage current flow.
If the PD-SOI MOS device
10
is incorporated within a logic circuit, the unexpected parasitic bipolar leakage current flow is known to cause an initial switching delay problem in the logic circuit as reported by Lu et al. in IEEE Journal of Solid State Circuits, vol. 32, no. 8, pages 1241-1253, August 1997. The delay problem only occurs during an activation of the logic circuit after the logic circuit has been idle for more than a few milli-seconds.
The problem is escalated when many devices, such as PD-SOI MOS device
10
, of the logic circuit have their sources connected together, such as in a multiplexing circuit. This causes a multiplication of the bipolar leakage current which slows down the switching speed when one of the MOS devices
10
in the multiplexing circuit is activated. This is because all of the generated bipolar leakage current from all the devices must be discharged through a single path, i.e., a path defined by a switch connected to ground (not shown).
The duration of the initial switching delay caused by the current flow depends on several factors, such as the gain of the parasitic bipolar device
80
underneath the body region
50
of the PD-SOI MOS device
10
, the threshold voltage of the PD-SOI MOS device
10
, the capacitance of the base-emitter junction of the PD-SOI MOS device
10
, the stress voltage level, i.e., Vdd, and the number of devices
10
connected together. It has been demonstrated that for an SRAM array, the parasitic bipolar leakage current causes the SRAM array to be up to 20% more slower, than if the leakage current was non-existent.
If the PD-SOI MOS device
10
is incorporated within an SRAM array, a transient bipolar effect is observed due to the parasitic bipolar leakage current as reported by Kuang et al. in IEEE Journal of Solid State Circuits, vol. 32, no. 6, pages 837-844, June 1997. The transient bipolar effect is caused by uneven body stress in the body region
50
of the PD-SOI MOS device
10
which causes a delay of a first write operation within the SRAM array.
The transient bipolar effect has more detrimental effects in an SRAM array utilizing Vdd sensing and having nMOS transfer devices, as opposed to an SRAM array utilizing ground sensing and having pMOS transfer devices. However, SRAM arrays utilizing Vdd sensing and having nMOS devices are more common in SRAM architecture systems, since an SRAM array utilizing Vdd sensing and having nMOS devices is faster than an SRAM array utilizing ground sensing and having pMOS devices due to faster electron mobility than hole mobility.
With reference to
FIG. 2
, there is illustrated a portion of an SRAM array, designated generally by reference numeral
200
, having one bitline BL connected to many SRAM cells, i.e., SRAM cells
210
,
220
,
230
. Each SRAM cell has a pair of transfer transistors
202
and back-to-back inverters
204
A and
204
B. The SRAM cells in the SRAM array
200
experience the worst transient behavior due to the transient bipolar effect when all the SRAM cells in the array
200
store “high” on one side, and the bitline BL is also precharged “high”. At this moment, all the body regions
50
of the transfer transistors
202
are charged up.
Hence, when writing “zero” to a selected SRAM cell, e.g., SRAM cell
210
, it will take 20% more time than if all the SRAM cells are stored with “low”. This is because, the collective burst of the parasitic bipolar current at the beginning of the first cycle from all the transfer transistors
202
, i.e., of all the unselected SRAM cells, e.g., SRAM cells
220
,
230
and
240
, must be discharged. Also, it should be noted that the body regions
50
of all the unselected transfer transistors
202
are not completely drained of the parasitic bipolar current during the first few cycles of accesses.
If the SRAM array
200
has been idle for a period of time, the body regions
50
of all the transistors
202
are fully charged. Now, when the array
200
is first accessed by activating, for example, the first wordline WL for writing a “low” data, at this moment, because the bitline BL drops from Vdd to ground, the parasitic bipolar leakage current from all the unselected transfer transistors
202
must be
Assaderaghi Fariborz
Hsu Louis L.
Joshi Rajiv V.
Saccamango Mary J.
Dilworth & Barrese LLP
Elms Richard
IBM Corporation
Nguyen Hien
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