Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-11-25
2001-05-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06226777
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to verification tools used for circuit design, and more particularly, to a method and system for improving the performance of a circuit design verification tool by extending a formal verification tool to perform an engineering change order (ECO) compile operation.
BACKGROUND OF THE INVENTION
Modem electronic circuit design in general, and application specific integrated circuit (ASIC) design in particular, typically begins with a circuit designer writing a high level code that represents the desired functionality of the circuitry. This high level code is typically written in a programming language such as VERILOG® (VERILOG® is a registered trademark of Cadence Design System Corp.), VHDL, (very high speed integrated circuit hardware description language), or C language. After the design has been through several iterations and exhibits a degree of stability, the high level description language code can be converted to logic level, which uses gate level logic such as NAND gates and NOR gates etc., to implement the desired functionality described in the aforementioned high level code. The tool that performs this conversion is known as a synthesis tool. Several available synthesis tools can perform this conversion. For example, a software package available from SynOpSys Inc., of 700 East Middlefield Road, Mountain View, Calif., can perform the conversion from high level code to logic level code. As is known to those skilled in the art, the high level code is referred to as register transfer language (RTL) netlist and the logic level code is known as the gate level netlist.
Once the high level code is converted to gate level code, the designer will typically perform additional testing via simulation and formal verification in order to verify that the logic level code is an accurate representation of the high level code. If the logic level code is successfully verified, the logic level code is converted to a detailed layout of the circuit and the circuit is fabricated.
Typically, a formal verification tool in the form of a software product, available from, for example, Chrysalis Symbolic Design, Inc., of 101 Billerica Avenue, North Billerica Mass. is used to compare the high level code (RTL netlist) to the logic level code (gate level netlist) to determine whether they are equivalent. Typically, the RTL netlist is compared to the gate level netlist.
Sometimes during the verification operation, the high level code is changed to implement design changes or revisions. If the change is significant (e.g., a full metal mask change), another gate level netlist is typically generated and another round of verification testing is performed to compare the revised high level code to the revised gate level code.
If a required change to the high level code is minor (e.g., a simple metal mask change) a simplified compiler operation may be performed, thus reducing cost and minimizing production delay. An ECO (engineering change order) compiler is available from for example, SynOpSys Inc. in the form of an ECO compiler. Unfortunately, the cost of the ECO complier is approximately the same as the cost of performing the original formal verification. This indicates that even for a small revision in the high level code, a designer must perform the compile operation and then perform the design verification operation, each operation adding cost and production delay. A shortcoming with this process is that the circuit designer must determine the gate level change corresponding to the high level code change using different and often incompatible tools, or do it purely manually, which is highly error prone. The designer must then perform the verification operation again to verify the equivalency of the revised gate level netlist to the revised RTL netlist.
Unfortunately, the above mentioned verification operation cannot determine the change required to the first gate level netlist to make it match the revised RTL netlist. This predicament requires that the circuit designer switch between the synthesis tool and the verification tool.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
The present invention provides a method and system for extending the application of a circuit design formal verification tool to add the functionality of a circuit design synthesis tool.
Briefly described, in architecture, the system can be implemented as follows. The system comprises a first high level circuit design program code (first RTL netlist) and a first logic level circuit design code (first gate netlist). Also included is a tool for comparing the first high level circuit design program code to the first logic level circuit design code in order to determine whether the first logic level circuit design code is an accurate representation of the first high level circuit design program code. If a problem with the first high level circuit design program code is discovered, then the first high level circuit design program code is revised. Also included is a compiler for compiling the revised high level circuit design program code in order to develop a revised logic level circuit design code.
The present invention can also be viewed as providing a method for improving a circuit design verification tool by integrating the operations of design comparison and design revision. In this regard, the method can be broadly summarized by the following steps: generating a first high level circuit design program code (first RTL netlist), generating a first logic level circuit design code (first gate netlist), comparing the first high level circuit design program code to the first logic level circuit design code in order to determine whether the first logic level circuit design code is an accurate representation of the first high level circuit design program code, and compiling a revised high level circuit design program code in order to develop a revised logic level circuit design code.
The present invention has numerous advantages, a few of which are delineated hereafter as merely examples.
An advantage of the invention is that it extends the usefulness of a circuit design formal verification tool.
Another advantage of the present invention is that it eliminates the need for a circuit designer to use multiple tools in order to implement changes to the design.
Another advantage of the invention is that it is simple in design, user friendly, robust, reliable, and efficient in operation, and easily implemented for mass commercial production.
Another advantage of the invention is that it adds the functionality of a compiler to a formal verification tool.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.
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Agilent Technologie,s Inc.
Kik Phallaka
Smith Matthew
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