Method and system for improving the latency in a data...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S052000, C710S310000

Reexamination Certificate

active

11095099

ABSTRACT:
A system for transferring packets between a packet transfer core and an application layer device over an application layer interface includes a buffer system disposed in the packet transfer core having an input for receiving packets from a packet source; an output for transferring packets to the application layer interface; a buffer device having an input coupled to the input of the buffer system and an output; a selection device having a first input coupled to the output of the buffer device, a control input and an output coupled to the output of the buffer system; and a bypass path coupled between the input of the buffer system and a second input of the selection device. The control input of the selection device receives a first wait signal from the application layer device which is not asserted in a first mode of operation and asserted in a second mode of operation. In the first mode of operation, packets are transferred from the input of the buffer system to the output of the buffer system via the bypass path and, in the second mode of operation, packets are transferred from the input of the buffer system to the buffer device, and are store in the buffer device without being transferred to the output of the buffer system until the first wait signal from the application layer device is deasserted.

REFERENCES:
patent: 6026451 (2000-02-01), Sreenivas
patent: 6715055 (2004-03-01), Hughes
patent: 6760793 (2004-07-01), Kelley et al.
patent: 6839784 (2005-01-01), Ennis et al.
patent: 2004/0010612 (2004-01-01), Pandya
patent: 2004/0151197 (2004-08-01), Hui
patent: 2005/0055489 (2005-03-01), Elliott
patent: 2005/0238038 (2005-10-01), Keller et al.
patent: 2006/0173970 (2006-08-01), Pope et al.
patent: 2006/0230210 (2006-10-01), Stanton
patent: 2006/0230215 (2006-10-01), Woodral
patent: 2006/0242354 (2006-10-01), Johnsen et al.
patent: 2006/0256879 (2006-11-01), Szczepanek et al.
patent: 2007/0011366 (2007-01-01), Morishita et al.
The Effective Buffer Architecture for Data Link Layer of PCI Express, IEEE 2004.
Definition of OSI Model from Wikipedia.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for improving the latency in a data... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for improving the latency in a data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for improving the latency in a data... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3773899

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.