Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-11-27
2004-06-29
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S153000, C711S173000, C709S215000
Reexamination Certificate
active
06757785
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to the field of computers, and, in particular, to computer memories. Still more particularly, the present invention relates to an improved method and system for improving the performance of cache memories in a multiprocessor computer system.
2. Description of the Related Art
Under a typical prior art method of utilizing cache memories in a multiprocessor computer system, common data used by multiple processors is mapped (cached) from a main memory to a cache memory of one or more of the multiple processors in the multiprocessor computer system. Under this traditional method of caching, initially each cache memory of each processor of the multiprocessor computer system may contain a valid copy of the common data. However, after a first processor writes an update to the common data into its cache, only that first processor's cache contains a valid copy of the common data. Whenever another processor needs to read or write to (change) the common data, it will “miss” the cached common data since the valid data is only in the first processor's cache. For example, in a multiprocessor computer having four processors, and assuming that the data is written to frequently, there is a 25% chance that the requesting processor will have the most current common data in its local cache, and thus a cache “hit” occurs when that common data is accessed. The same probability states that there is a 75% chance that the most current common data being requested will be in the cache of one of the other three processors, and thus the requesting processor will incur a cache “miss.” A cache “miss” requires the requesting processor to then “snoop” the caches of the other processors for the requested common data, or to go to main memory if none of those caches have the requested data. The description and percentages above assume that each processor has previously cached and is able to change the requested data.
SUMMARY OF THE INVENTION
The present invention recognizes the need to improve the hit ratio of a cache memory in a multiprocessor computer. The present invention therefore is a method and system for allocating and storing data to the cache memory in each processor in a multiprocessor computer system. Data structures in a main memory are partitioned into substructures that are classified as either exclusive substructures or sharing substructures. The exclusive substructures are cached exclusively by a specified processor, and the sharing substructures are cached by specified groups of processors in the multiprocessor computer. The classified partitioning results in an improved cache hit ratio compared to cache hit ratios found in standard caching schemes. This improvement over standard caching schemes becomes greater as the number of processors in the multiprocessor computer increases.
The above, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5210844 (1993-05-01), Shimura et al.
patent: 5634111 (1997-05-01), Oeda et al.
patent: 6021468 (2000-02-01), Arimilli et al.
patent: 6088770 (2000-07-01), Tarui et al.
patent: 6105112 (2000-08-01), Arimilli et al.
patent: 6314501 (2001-11-01), Gulick et al.
patent: 6360303 (2002-03-01), Wisler et al.
patent: 6370622 (2002-04-01), Chiou et al.
Brutman Michael Brian
Majd Mahdad
Bracewell & Patterson LLP
Peugh Brian R.
Sparks Donald
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