Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2001-09-14
2004-12-07
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S105000, C710S052000, C370S912000
Reexamination Certificate
active
06829667
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates in general to the field of central processor unit (CPU) intensive communication protocols. Particularly, this invention pertains to achieving increased instances of protocol processing for CPU intensive communications protocols.
2. General Background and Related Art
Communications systems employing modern digital communications protocols convey information in the form of messages, frames and/or packets made up of digital data. Each such message, frame and/or packet comprises various fields containing control information, message data, etc. relevant to an appropriate layer in the Open Systems Interconnection (OSI) model—a standard reference model describing the layers of a network and the types of functions expected at each layer. For example, at Layer
1
or the physical layer information is transmitted in the form of frames made up of bits; packets comprising one or more frames of fields and data are transmitted at Layer
2
or the data link layer in the OSI model; and messages comprising one or more packets of fields and data are transmitted at Layer
3
or the network layer in the OSI model. The final processing of one or more messages, frames and/or packets result in one or more messages for use by higher layers in the OSI model.
In a typical communications system, each frame receipt and transmission has to be processed by a specialized protocol processing device. The frame information is conveyed to the main CPU core by generating an interrupt. The CPU core stops its normal processing and services on occurrence of the interrupt, takes care of the protocol condition and then resumes normal processing and services. Thus the transmission and reception of data frames results in interrupts of the CPU for each frame sent or received. For some CPU intensive networking protocols such as the Signaling System 7 (SS7) protocol, data in the form of frames comes in continuously and places a high demand on a CPU to process the data by interrupting the CPU for every frame received or transmitted. Typically, some of those protocols maintain a communication channel open by sending frames continuously to monitor the integrity of a signaling link, such as Link Status Signaling Units (LSSUs) which are used to bring a link into alignment as part of the SS7 protocol. Also, some protocols send idle frames when there is no data to transmit such as Fill In Signaling Units (FISUs) sent as part of the SS7 protocol. These FISUs are 6 byte signal units that comprise, among other things, the sequence numbers denoting the last valid frame received/transmitted and the next frame to be transmitted. Each FISU and LSSU has to be processed the same way as frames containing message data thereby taxing the CPU's processing capabilities. Moreover, FISUs and LSSUs often don't contain any new information thereby making CPU processing redundant.
Consequently, even the most powerful CPU often gets overloaded trying to service such processing intensive communications protocols such as SS7. This overloading of a CPU often limits the number of data links the CPU can support. For this reason, very few data channels (typically 3-16 channels) running such processing intensive protocols can be supported by traditional systems. In the present state-of-art, there appear to be no single board solutions for the SS7 protocol servicing 64-128 channel signaling data links.
Accordingly, there is a need in the art for a solution to achieving increased instances of protocol processing for CPU intensive communications protocols, preferably utilizing existing hardware components. Therefore, it is advantageous to provide a method and system for improved processing of CPU intensive communications protocols.
REFERENCES:
patent: 4959781 (1990-09-01), Rubinstein et al.
patent: 5740451 (1998-04-01), Muraki et al.
patent: 6092160 (2000-07-01), Marsters
“Design and implementation of interrupt packaging mechanism” by Nakashima, K. ; Kusakabe, S. ; Taniguchi, H. and Amamiya M (abstract only).*
“Resource management of the OS network subsystem” by Ghosh, S and Rajkumar, R. R. (abstract only).
Intel Corporation
Pillsbury & Winthrop LLP
Ray Gopal C.
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