Method and system for implementing timing analysis and...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization

Reexamination Certificate

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C716S113000, C716S115000

Reexamination Certificate

active

07930675

ABSTRACT:
Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.

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U.S. Appl. No. 11/621,915, filed Jan. 9, 2007.
U.S. Appl. No. 11/733,749, filed Apr. 10, 2007.

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