Method and system for implementing stacked vias

Details Method and system for implementing stacked vias Method and system for implementing stacked vias

2007-12-27

2011-10-18

Garbowski, Leigh (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Layout editor

C716S100000

Reexamination Certificate

active

08042088

ABSTRACT:
The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element.

REFERENCES:
patent: 5481473 (1996-01-01), Kim et al.
patent: 5604680 (1997-02-01), Bamji et al.
patent: 5731986 (1998-03-01), Yang
patent: 6671869 (2003-12-01), Davidson et al.
patent: 6910200 (2005-06-01), Aubel et al.
patent: 7024652 (2006-04-01), McGaughy et al.
patent: 7334206 (2008-02-01), Dinter et al.
patent: 7409666 (2008-08-01), Almeida et al.
patent: 7555739 (2009-06-01), Ginetti et al.

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