Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-28
2009-12-08
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07631289
ABSTRACT:
Disclosed is an improved method and system for creating lithography models. According to some approaches, a new method and system is disclosed for determining the number of matrices to use for representing an optical lithographic model. The approach is based upon a selected accuracy level, instead of requiring the user to select the number of matrices that is desired as was employed in the prior art. The method and system will then determine the number of matrices to use to support the accuracy that is desired.
REFERENCES:
patent: 7079223 (2006-07-01), Rosenbluth et al.
patent: 7342646 (2008-03-01), Shi et al.
patent: 2005/0091631 (2005-04-01), Gallatin et al.
patent: 2006/0282814 (2006-12-01), Percin et al.
patent: 2007/0032896 (2007-02-01), Ye et al.
patent: 2007/0234246 (2007-10-01), Sinha et al.
patent: 2008/0127027 (2008-05-01), Gallatin et al.
Cadence Design Systems Inc.
Vista IP Law Group LLP
Whitmore Stacy A
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