Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2000-01-07
2003-12-30
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S136000, C711S134000
Reexamination Certificate
active
06671766
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the storage of disk tracks in a cache. More particularly, the present invention relates to a method and system for efficiently aging cached tracks.
2. Description of Related Art
With the reduced cost of memory chips, cache sizes have increased into the tens of gigabytes. While this has allowed improved disk subsystem performance by increasing cache hits for larger working sets and workloads, the amount of controller memory required to manage this amount of cache has also increased accordingly. Even though the cost of memory is declining, there are two good reasons for minimizing the amount of controller memory required to support large cache sizes. First, it is still desirable to minimize the amount of controller memory needed for the subsystem since this cost is a constant that is invariant with the size of the customer purchased cache size. A memory size required to handle the largest cache size may be a price barrier to an entry-level subsystem that has a small amount of cache. Second, due to the legacy of subsystems already in the field, the requirement to increase the controller memory just to increase cache size results in a significant increase to the installation cost, with the added expense of controller memory upgrade kits.
For current subsystems, the amount of controller memory required to manage 3 gigabytes of cache is 2304 kilobytes. A cache of 6 GB will require 4608 KB of controller memory. This amount of memory is not available on some current subsystems.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for memory efficient track aging. Each time a track is referenced, a value representing the reference age is entered for a track entry in a last referenced age table (LRAT). A reference age is not a real age but merely a relative age between the two preset values. The last referenced age table is indexed by track. A second table, an age frequency table (AFT), counts all segments in use in each reference age. The AFT is indexed by the reference age of the tracks. When a track is referenced, the number of segments used for the track is added to a segment count associated with the last referenced age of the track. The segment count tallies the total number of segments in use for the reference age for all tracks referenced using that age. The number of segments used for the previous last referenced age of the track is subtracted from the segment count associated with the previous last referenced age in the AFT. When free_space is needed, tracks are discarded from the LRAT by reference age, the oldest first. The range of ages to be discarded in the LRAT is calculated in the AFT by counting the total amount of segments used by each reference age until the total number of segments needed to bring the free_space back into a threshold range is realized. Counting is started at the AFT entry with the oldest reference age. The reference age of the last counted entry in the AFT is the discard age. The LRAT is scanned for reference ages between the old age and the discard age and those reference ages are discarded.
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“Implementing Global Memory Management in a Workstation Cluster”; Operating Systems Review (SIGOPS), US, ACM Headquarter, New York, vol. 29, No. 5, Dec. 1, 1995.
Milillo Michael Steven
Peterson Gregory William
Vandenbergh Henk
Anderson Matthew D.
Carstens Yee & Cahoon LLP
Kim Matthew
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