Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
2006-02-09
2008-11-25
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S005000
Reexamination Certificate
active
07457937
ABSTRACT:
Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which comprises a plurality of memory modules disposed as an array of parallel columns. In response to receiving an indication that said plurality of instances of data is being accessed as a row of data, a first address translation table is accessed which describes the same row address in each of said plurality of memory modules wherein an instance of data is stored. Then, in response to receiving an indication that said plurality of instances of data is being accessed as a column of data, a second address translation table is accessed which describes a successive row address in each successive memory module wherein an instance of data is stored.
REFERENCES:
patent: 4799149 (1989-01-01), Wolf
patent: 5177704 (1993-01-01), D'Luna
patent: 5481487 (1996-01-01), Jang et al.
patent: 5594854 (1997-01-01), Baldwin et al.
patent: 5623692 (1997-04-01), Priem et al.
patent: 5664162 (1997-09-01), Dye
patent: 5854637 (1998-12-01), Sturges
patent: 5911144 (1999-06-01), Schwartz et al.
patent: 5915255 (1999-06-01), Schwartz et al.
patent: 5920876 (1999-07-01), Ungar et al.
patent: 6038572 (2000-03-01), Schwartz et al.
patent: 6055545 (2000-04-01), Yazaki et al.
patent: 6105114 (2000-08-01), Okuno
patent: 6115782 (2000-09-01), Wolczko et al.
patent: 6172687 (2001-01-01), Kitamura et al.
patent: 6188394 (2001-02-01), Morein et al.
patent: 6249853 (2001-06-01), Porterfield
patent: 6327000 (2001-12-01), Auld et al.
patent: 6366289 (2002-04-01), Johns
patent: 6833835 (2004-12-01), Van Vugt
patent: 7158148 (2007-01-01), Toji et al.
patent: 2006/0010181 (2006-01-01), Elftheriou et al.
Cheng Christopher T.
Purcell Stephen C.
Nvidia Corporation
Peugh Brian R
LandOfFree
Method and system for implementing low overhead memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for implementing low overhead memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for implementing low overhead memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4023803