Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-27
2010-10-05
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07810056
ABSTRACT:
A method and system for implementing context aware synthesis of assertions is disclosed. The method and system for assertion synthesis includes converting an assertion formula to sequence implication form using semantic preserving rewrite rules, performing optimizations on the resulting formula to reduce the number of state-bits in a final FSM (Finite State Machine), and synthesizing the resulting formula to the final FSM using context aware sequence synthesis.
REFERENCES:
patent: 5987239 (1999-11-01), Kirsch
patent: 6591403 (2003-07-01), Bass et al.
patent: 6651228 (2003-11-01), Narain et al.
patent: 6742166 (2004-05-01), Foster et al.
patent: 7188324 (2007-03-01), Qiu et al.
patent: 7313772 (2007-12-01), Hekmatpour et al.
patent: 7325209 (2008-01-01), Mitra et al.
patent: 7340700 (2008-03-01), Emerson et al.
patent: 7386813 (2008-06-01), Singh et al.
patent: 7421668 (2008-09-01), Ip et al.
patent: 7454324 (2008-11-01), Seawright et al.
patent: 7596770 (2009-09-01), Kuehlmann et al.
patent: 7603636 (2009-10-01), Yamada
patent: 2003/0018945 (2003-01-01), Foster et al.
patent: 2006/0271890 (2006-11-01), Hekmatpour et al.
patent: 2006/0271904 (2006-11-01), Emerson et al.
patent: 2007/0074137 (2007-03-01), Nishida et al.
patent: 2008/0015838 (2008-01-01), Stern
patent: 2008/0066030 (2008-03-01), Hekmatpour et al.
patent: 2008/0072196 (2008-03-01), Hekmatpour et al.
patent: 2008/0104556 (2008-05-01), Yamada
patent: 2009/0144680 (2009-06-01), Lehavot et al.
patent: 2006285626 (2006-10-01), None
patent: 2006035854 (2006-04-01), None
Accellera “Property Specification Language Reference Manual Version 1.1”, Jun. 2004, pp. 1-131, located at http://www.eda.org/vfv/docs/PSL-v1.1.pdf.
Accellera “SystemVerilog 3.1a Language Reference Manual,” Accellera's Extensions to Verlog, May 2004, pp. 1-568 located at http://www.eda.org/sv/SystemVerilog—3.1a.pdf.
Barrione et al., “On-line Asertion-Based Verification with Proven Correct Monitors”, ITI 3rd International Conference on Information and Communications Technology, Dec. 5-6, 2005, pp. 125-143.
Beer, I et al. “On-the-fly model checking of RCTL formulas” 10th International Conference on Computer Aided Verification (CAV '98), 1998, pp. 1-12, located at http://www.research.ibm.com/haifa/projects/verification/RB—Homepage/ps/ag-bool—f.ps.
Beer et al., “The Temporal Logic Sugar”, 13th Conference on Computer-Aided Verification, Jul. 2001, pp. 363-367.
Ben-David, S. et al. “Automata construction for regular expressions in model checking” pp. 1-12, located at http://www.wisdom.weizmann.ac.il/{dana/publicat/pos-nfa.pdf.
Datta, K. et al. “Assertion based verfication using HDVL” Proceedings of the 17th International Conference on VLSI Design, Mumbai, India, Jan. 5-9, 2004, pp. 319-325.
Gawanmeh, A. et al., “Embedding and Verification of PSL Using AsmL”, Proceedings of the International Conference on Abstract State Machines (ASM'05), Mar. 2005, pp. 201-216, Paris, France.
Gheorghita, S. V. et al., “Constructing Checkers From PSL Properties”, Proceedings of the 15th International Conference on Control Systems and Computer Science May 2, 2005, pp. 757-762, ES [06.11], The Netherlands.
Gordon, M.J.C. “Validating the PSL/sugar semantics automated reasoning” Formal Aspects of Computing, Springer-Verlag, UK, Dec. 2003, vol. 15, No. 4, pp. 406-421.
Habibi et al., “On the Design and Verification Methodology of the Look-Aside Interface”, 2005 Proceedings of Design, Automation and Test Confernece in Europe, Mar. 7-11, 2005, vol. 3, pp. 290-295.
Habibi et al., “Towards an Efficient Assertion Based Verification of SystemC Designs”, Ninth IEEE International High-Level Design Validation and Test Workshop, Nov. 10-12, 2004.
Habibi et al., “Design for Verification of SystemC Transaction Level Models”, Proceedings of Design, Automation and Test in Europe, vol. 1, Mar. 7-11, 2005, pp. 560-565.
Hopcroft, J. et al., “Introduction to Automata Theory, Languages, and Compuatation”, 2nd edition.
Kamel et al., “Redundancy: An Approach to the Efficient Implementation of Semantic Integrity Assertions”, Proceedings of the 23rd Annual Hawaii International Conference on Systems Sciences, vol. 2, Jan. 2-5, 1990, pp. 393-399.
Maidl, M. “Common fragment of CTL and LTL” Proceedings of the 2000 IEEE Annual Symposium on Foundations of Computer Science, Los Alamitos, CA 2000, pp. 643-652.
Massonet et al., “Analogical Reuse of Requirements Frameworkds,” Proceedings fo the Third IEEE International Symposium on Requirements Engineering, Jan. 6-10, 1997, pp. 26-37.
Morin-Allory et al., “Asynchronous Assertion Monitors for Multi-Clock Domain System Verification”, Seventeenth IEEE International Workshop on Rapid System Prototyping, Jun. 14-16, 2006, pp. 98-102.
Pacholik, A; et al., “Real Time Constraints in System Level Specifications Improving the Verificatoin Flow of Complex Systems”, In: Proceedings of Net.ObjectDays 2005, Sep. 19-22, 2005, pp. 283-294.
Ruah, S. et al. “Automata construction for on-the-fly model checking PSL safety simple subset”pp. 1-22, located at http://www.wisdom.weizmann.ac.il/{dana/publicat/sefety—psl—det.pdf.
Somenzi, F. “Efficient Buchi Automata from LTL Formulae”, CAV'00, pp. 248-263, 2000.
Tuerk, T. et al., “From PSL to LTL: A Formal Validation in HOL”, Proceedings of the International Conference on Theorem Proving in Higher Order Logics (TPHOL), Aug. 22, 2005, pp. 342-357, Springer-Verlag, Germany.
Supplemental Search Report dated Mar. 1, 2007 for European Applicaton No. 05852297.0.
Non-Final Office Action dated May 29, 2009 for U.S. Appl. No. 11/712,003.
Garg Tarun
Singh Vinaya Kumar
Cadence Design Systems Inc.
Dinh Paul
Vista IP Law Group LLP
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