Method and system for implementing a floating point compare...

Details Method and system for implementing a floating point compare... Method and system for implementing a floating point compare...

2006-05-02

2006-05-02

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

Reexamination Certificate

active

07039792

ABSTRACT:
A method and system for implementing a floating point compare operation in an x86 compatible processor. The method includes the step of comparing a first bit pattern and a second bit pattern using a floating point unit of an x86 compatible processor. The EFLAGS register is set in accordance with a result of the comparison. A sign flag and an overflow flag of the EFLAGS register are encoded with information derived from the result of the comparison.

REFERENCES:
patent: 6247117 (2001-06-01), Juffa
patent: 6393555 (2002-05-01), Meier et al.
patent: 6934832 (2005-08-01), Van Dyke et al.

Affiliated with

Also associated with

Rating

Method and system for implementing a floating point compare... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for implementing a floating point compare..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for implementing a floating point compare... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3588884