Method and system for identifying tested path delay faults

Details Method and system for identifying tested path delay faults Method and system for identifying tested path delay faults

1997-10-23

2000-10-10

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 6, 703 13, 703 19, G06F 1750

Patent

active

061311812

ABSTRACT:
The present invention relates to a method and system for identifying tested path-delay faults in integrated circuits. A path status graph is generated to represent the detected status of simulated path-delay faults. The path status graph includes vertices representing primary inputs, primary outputs and elements of the circuit. Detected status path-delay faults can be dynamically distributed to edges of the path status graph. Tested path-delay faults can be identified from traversal of the edges of the path status graph.

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