Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-26
2003-10-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06637012
ABSTRACT:
The present invention generally relates to identifying selected electronic logic gates in very large scale integrated (“VLSI”) chips. More specifically, it relates to an improved method and system for identifying field effect transistors (“FETs”) implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity.
Computer aided design (“CAD”) systems that design electronic circuits, often referred to as Electronic CAD (“ECAD”) tools, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. The design process has now become so complex that the current generation of integrated circuit (IC) chips, particularly in the case of VLSI chips, often cannot be designed without the help of ECAD tools. ECAD tools are ideally suited to performing tasks implemented in the circuit design process as they can break down large, complicated circuits into a plurality of circuits of relatively simpler functionality. The ECAD tools can then iteratively lay out these much simpler circuits and achieve the desired overall design of the desired large complicated circuit.
In performing a circuit design task, the ECAD tool generally allows for an user to schematically create and/or edit circuit designs by graphically placing and connecting circuit components, which can be represented as objects by the ECAD tool. The ECAD tool performs calculational circuit design and evaluation tasks for the schematic circuit, such as optimizing the circuit, testing the circuit through simulation modeling, and the like. As represented by the ECAD tool, the circuit may comprise a plurality of “nets,” with each net representing a connection between the terminals of two transistors. A net may also be referred to as a signal. An ECAD tool also typically generates a “netlist,” which is a list of a group of logically related nets, including connectivity data for each. The netlist may be in the form of a database. Also, the netlist may describe a multiplicity of nets that can number into the millions for VLSI chips. As a result, netlists can be of enormous size and complexity.
Different types of sub-tools of an ECAD tool may be used in IC design/evaluation tasks. In particular, ECAD tools can be used to identify the topology of a design stored on a netlist by identifying constituent FETs that comprise logic gates. A FET is defined as a transistor with a region of donor material with two terminals called the “source” and the “drain”, and an adjoining region of acceptor material between, called the “gate”. The voltage applied between the gate and the substrate controls the current flow between source and drain by depleting the donor region of its charge carriers to greater or lesser extent. There are generally two kinds of FETs: Junction FETs, (i.e., a FET in which the conducting channel lies between PN junctions in the silicon material. A PN junction acts as a diode, so it becomes conductive if the gate voltage gets reversed) and Metal Oxide Semiconductor FETs (“MOSFETs”) (i.e., a FET in which the conducting channel is insulated from the gate terminal by a layer of oxide. Therefore, it does not conduct even if a reverse voltage is applied to the gate). A design may have thousands or millions of FETs on the chip, which makes it impractical to identify the topologies without the use of automated methods.
Current methods for identifying MOSFETs (“FETs”) implemented in a predefined logic equation requires multiple circuit recognition schemes to be used. In particular, a circuit recognition scheme for each type of logic (e.g., NAND, NOR, AND, OR, etc.) must be separately detected. The alogorithm for identifying these FETs are typically implemented inside another ECAD tool for circuit analysis. Since the FETs used with each type of logic gate are identified separately, arbitrary functions cannot be recognized by these prior ECAD tools. Thus, there is a need for an improved method for identifying topologies of chip designs.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to an improved method and system for identifying selected logic functions in the topologies of a chip design. More specifically, it relates to an improved method and system for identifying FETs associated with a predefined logic equation defined by at least one signal name from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity.
The present invention provides a method that includes the steps of selecting an output node from the netlist, preparing the predefined logic equation for searching FETs in the netlist, and identifying FETs from the netlist that are implemented in the prepared predefined logic equation.
The present invention also provides a computer system that includes a storage medium, a processor for executing a program stored on the storage medium for identifying FETs implemented in a predefined logic equation from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity. The program that includes a set of instructions for selecting an output node from the netlist, preparing the predefined logic equation for searching FETs in the netlist, and identifying FETs from the netlist that are implemented in the prepared predefined logic equation.
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Keller S. Brandon
Rogers Gregory Dennis
Dimyan Magid Y
Hewlett--Packard Development Company, L.P.
Siek Vuthe
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