Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-09-09
1998-10-13
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711150, 711151, G06F 1200
Patent
active
058227580
ABSTRACT:
A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information. In the second aspect, first logic coupled to the storage unit determines the priority of each of the plurality of events in response to the first signal and outputs a second signal indicating the priority of each event. Second logic coupled to the first logic grants access to the cache in response to the second signal.
REFERENCES:
patent: 4953081 (1990-08-01), Feal et al.
patent: 5485455 (1996-01-01), Dobbins et al.
patent: 5513335 (1996-04-01), McClure
patent: 5689656 (1997-11-01), Baden et al.
Elliott Timothy Alan
Loper Albert John
Olson Christopher Hans
Shippy David J.
International Business Machines - Corporation
Rockett Esteban A.
Salys Casimer K.
Swann Tod R.
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