Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-03
2003-03-18
Flynn, Nathan J. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06536023
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the present invention relates to electronic design automation and, more particularly, to methods and systems for conducting metal-end, enclosure, and exposure checks of vias through an electronic design automation procedure.
2. Background
Chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation and verification of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer builds up a circuit by inputting information at a computer workstation generally having high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's specifications). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. After this specific cell-to-cell connectivity has been established, the physical design and layout software creates a physical layout file of the integrated circuit, including the physical position of each metal line (i.e., wire) and each via (i.e., metal transition between chip layers). As a last step before creation of the mask file for delivery to the fabrication facility, the physical verification and layout validation software performs several design rule checks (DRCs) on the layout file. Collectively, these DRCs constitute what is generally referred to in the industry as the “Rule Deck.”
During the design rule checks contained in the Rule Deck, the physical layout file generally must be checked for correct relative positioning of vias and metal lines. For example, to ensure adequate contact between vias and metal lines (when a conductive path between the via and metal line is called for), minimum overlap distances are required which dictate the extent to which the metal must extend beyond each via. These minimum overlap distances often vary depending on the shape of the metal surrounding the via. As another example of a design rule check, certain minimum distances are required between vias and metal ends, so as to reduce the likelihood of short circuits or other similar problems in the final product. Metal ends are generally defined as the terminating edge(s) or point(s) of metal lines. Minimum distances are also required for vias enclosed by metal (also referred to as vias at enclosures). Enclosures are generally defined as connection points between vias and metal, which are not at a metal end (i.e., where the footprint of the via on the metal is near no more than two metal edges). Another design rule check relates to exposure, whereby a determination is made as to whether all or part of a via is exposed, i.e., not covered by metal.
In conventional techniques, all vias are checked by design rules checks (DRCs) which are part of the Rule Deck. As part of these procedures, for each metal end, the distance from each point at the edge of the metal end to each via is calculated to ensure that minimum distances are met. The calculations required by these procedures easily number in the millions. Many of these calculations are unnecessary, however, because they are performed on vias that are obviously far from metal edges. As a result, a great deal of processing time is wasted.
Accordingly, the inventors have determined that it would be advantageous to provide an intelligent selection of which vias should have the complete design rule checks performed on them, while screening out vias that do not require a complete set of design rule checks.
SUMMARY OF THE INVENTION
The invention provides in one aspect systems and methods for selecting a subset or subsets of vias on which to perform metal end, enclosure and exposure checks.
In a preferred embodiment, an automated design rule checking software system receives as an input a physical layout file for a circuit design. The automated design rule checking software system outputs a list of vias needing design rule checks for violations in up to three categories: metal end, enclosure and exposure.
In one or more embodiments, an automated process selects vias from a physical layout file likely to cause design rule check problems, from among all of the vias in the physical layout file. The process then selects those vias that violate the enclosure rule and performs a design rule check for enclosure violations on the identified vias; performs a design rule check for metal end violations on the potentially problematic vias; and performs an exposure check on the potentially problematic vias.
Potentially problematic vias may be identified by expanding the dimensions of existing vias by a first predetermined minimum distance, subtracting out the metal area, and identifying those vias with residual portions remaining as potentially problematic vias. Candidate vias for an enclosure design rule check may be identified by expanding the dimensions of potentially problematic vias by a second predetermined minimum distance, subtracting out the metal area, and identifying those vias with residual portions remaining as violating the enclosure design rules. Candidate vias for a metal end design rule check may be identified by expanding the dimensions (excluding the corner regions) of potentially problematic vias by the first predetermined minimum distance, subtracting out the metal area, and identifying those vias with residual portions remaining as violating the metal end design rules.
Further embodiments, modifications, variations and enhancements are also described herein.
REFERENCES:
patent: 5581475 (1996-12-01), Majors
patent: 5812415 (1998-09-01), Baisuck
patent: 6275971 (2001-08-01), Levy et al.
Pleskacz et al., “A DRC-Based Algorithm for Extraction of Critical Areas for Opens in Large VLSI Circuits,” IEEE Trans. on CAD of ICs and Systems, vol. 18, No. 2, Feb. 1999, pp. 151-162.*
Jeppson et al., “Formal Definitions of Edge-Based Geometric Design Rules,” IEEE Trans. on CAD of ICs and Systems, vol. 12, No. 1, Jan. 1993, pp. 59-69.*
Jeppson et al. “Formal Definitions of Edge-Based Geometric Design Rules,” IEEE Trans. On CAD of Ics and Systems, vol. 12, No. 1, Jan. 1993, pp. 59-60.
Mohan Muni B. S.
Moynihan Kevin E.
Cadence Design Systems Inc.
Flynn Nathan J.
Garbowski Leigh Marie
Lyon & Lyon LLP
LandOfFree
Method and system for hierarchical metal-end, enclosure and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for hierarchical metal-end, enclosure and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for hierarchical metal-end, enclosure and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3032753