Method and system for hardware implementation of resetting...

Details Method and system for hardware implementation of resetting... Method and system for hardware implementation of resetting...

2007-02-09

2009-10-27

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

07610439

ABSTRACT:
Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

REFERENCES:
patent: 6765543 (2004-07-01), Masuda et al.
patent: 6798434 (2004-09-01), Shibata et al.
patent: 6829003 (2004-12-01), Takami
patent: 2001/0048466 (2001-12-01), Takami
patent: 2003/0184642 (2003-10-01), Shibata et al.
patent: 2004/0233189 (2004-11-01), Masuda et al.

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