Method and system for hardware implementation of resetting...

Details Method and system for hardware implementation of resetting... Method and system for hardware implementation of resetting...

2011-03-15

2011-03-15

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711SE12008, C713S500000

Reexamination Certificate

active

07908428

ABSTRACT:
Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

REFERENCES:
patent: 6081889 (2000-06-01), Kitao

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