Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-14
2007-08-14
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
10972361
ABSTRACT:
A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral HDL may be translated into a form that can be executed on a reconfigurable hardware platform. A set of compilation transforms are provided that convert behavioral constructs into RTL constructs that can be directly mapped onto an emulator. Such transforms are provided by introducing the concepts of a behavioral clock and a time advance finite state machine (FSM) that determines simulation time and sequences concurrent computing blocks in the DUT and the testbench.
REFERENCES:
patent: 5555201 (1996-09-01), Dangelo et al.
patent: 2004/0111252 (2004-06-01), Burgun et al.
patent: 2005/0198606 (2005-09-01), Gupta et al.
Mike Santarini of EE Times entitled Testbench Integrated on Emulator (May 24, 2004), printed Jul. 27, 2004, 3 pages, http://www.eedesign.com
ews/showArticle.jhtml?articleId=20900488&kc=4217, San Jose, California.
Mike Santarini of EE Times entitles Axis Adds Assertion Checking to Emulation/Acceleration (Aug. 19, 2002), printed Jul. 27, 2004, 4 pages, http://www.eedesign.com
ews/showArticle.jhtml?articleId=17407909&kc=4217.
Mike Santarini of EE Times entitled Axis' Xtreme Gets Behavioral Boost (Oct. 18, 2001), printed Jul. 27, 2004, 2 pages, http://www.us.design-reuse.com
ews
ews332.html.
Xtreme-II: The First Verification Environment for Platform Verification, printed Jul. 27, 2004, 3 pages, http://www.verisity.com/products/xtremeii.html.
Testbench Acceleration: Synthesizing e Testbenches Using Versity's eCelerator, printed on Jul. 27, 2004, 6 pages, http://www.verisity.com/resources/whitepaper/accelration.html.
Accelerated Verification Process Automation, printed on Jul. 27, 2004, 6 pages, http://www.verisity.com/resources/whitepaper/spextreme.html.
SpeXtreme: VPA System for High Performance Chip- and System-Level Verification, printed on Jul. 27, 2004, 2 pages, http://www.verisity.com/products/spextreme.html.
Daw Jyotirmoy
Gupta Sanjay
Krishnamurthy Suresh
Do Thuan
Mentor Graphics Corporation
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