Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-02-28
2006-02-28
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S720000, C714S723000, C711S113000, C711S118000
Reexamination Certificate
active
07007210
ABSTRACT:
The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be replaced by an operator when certain level of bit errors is reached. When a hard error exists on a cache address for the first time, serviceable first hard error, that cache line is deleted. Thus the damaged memory device is no longer used by the system. As a result, the system is running with “N−x” lines wherein “N” constitutes the total number of existing lines and “x” is less than “N”. An alternative method is to exchange the damaged memory device to a spare memory device. In order to provide such services, the system must first differentiate whether an error is a soft or hard error.
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Fields, Jr. James Stephen
Kitamorn Alongkorn
Lemmon Wayne
Lewis David Otto
Reick Kevin F.
Chung Phung My
International Business Machines - Corporation
McBurney Mark E.
Mok Wing Yan
Yee Duke W.
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