Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-12-17
2000-02-08
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711136, 711159, 711160, 711133, G06F 1200, G06F 1300
Patent
active
060237473
ABSTRACT:
A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received at the cache. In response to receipt of the first cache operation request, which specifies a particular entry among the plurality of entries, a single access of a coherency state associated with the particular entry is performed. Thereafter, in response to receipt of the second cache operation request, a determination is made whether servicing the second cache operation request requires replacement of one of the plurality of entries. In response to a determination that servicing of the second cache operation request requires replacement of one of the plurality of entries, an entry is identified for replacement. If the identified entry is the same as the particular entry specified by the first cache operation request, the identified entry is replaced only after servicing the first operation request. The replacement of the identified entry includes writing contents of the identified entry into a lower level memory in association with an updated coherency state derived from the coherency state obtained during the single access. In this way, the second cache operation request can be serviced without again accessing the coherency state of the identified entry.
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Dillon Andrew J.
Emile Volel
International Business Machines - Corporation
Russell Brian F.
Thai Tuan V.
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