Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2011-08-16
2011-08-16
Cleary, Thomas J (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S267000, C712S013000, C712S015000
Reexamination Certificate
active
08001308
ABSTRACT:
A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores.
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Rothman Michael A.
Zimmer Vincent J.
Cleary Thomas J
Intel Corporation
Stutman Joni D.
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