Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-12
2003-06-10
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C706S013000
Reexamination Certificate
active
06578176
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention pertains to the field of integrated circuit design optimization using electronic design automation tools. More particularly, aspects of the present invention pertain to a power dissipation optimization process for use in the design of complex integrated circuits with electronic design automation (EDA) tools.
BACKGROUND OF THE INVENTION
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems deliver the expected performance and obey the properties that their designers intended. As each successive generation of computer and software implemented systems and processes become more powerful, the task of designing and fabricating them becomes increasingly difficult.
Increasing levels of integration allow much higher circuit densities per integrated circuit die. Higher circuit densities allow higher operating speeds. During the operation cycle of a high-density integrated circuit, a certain amount of power will be drawn by the integrated circuit. This amount of power depends upon the types of operations the circuit is performing. For example, operations requiring large amounts of switching produce correspondingly large amounts of power dissipation.
Hence, the power dissipation experienced by the integrated circuit varies over time as the integrated circuit functions. During certain operations, the integrated circuit will experience peak power dissipation, where the amount of power dissipated by the circuit per unit of time is at maximum. Peak power affects the amount of heat generated by the integrated circuit. Peak power typically equates to peak heat generation, and thus, peak power characteristics are among the most important design constraints for new integrated circuit devices.
The design and manufacture of increasingly complex integrated circuits involves extensive use of CAD tools. The development of ASICs (application specific integrated circuits) and other complex integrated circuits using CAD tools is referred to as electronic design automation, or EDA. The design, checking, and testing of large-scale integrated circuits are so complex that the extensive use of CAD and EDA tools are required for realization of modern, complex integrated circuits.
The development of a new integrated circuit device begins with a design phase involving extensive use of EDA tools to facilitate various aspects of designing the new integrated circuit device. Typically, EDA tools function in part by decomposing the overall desired behavior of the integrated circuit into simpler functions which are more easily manipulated and processed. The EDA tool performs considerable computation to generate an efficient layout of a resulting “network” of design elements (e.g., logic gates, storage elements, etc.). The resulting network, commonly referred to as a netlist, comprises a detailed specification defining the integrated circuit, typically in terms of a particular fabrication technology (e.g., CMOS). The netlist can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Netlists for integrated circuit designs can represent a particular integrated circuit in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. The HDL description is used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a “silicon compiler” or “design compiler”). The compiler program processes the HDL description of the integrated circuit and generates therefrom a low-level netlist comprised of detailed lists of logic components and the interconnections between these components. The components specified by the netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections. In recent years the design process has become increasingly powerful and sophisticated, yielding very large, very complex high density integrated circuit devices.
Increasing levels of integration allow much higher circuit densities per integrated circuit die. Higher circuit densities allow higher operating speeds. During the operation cycle of a high-density integrated circuit, a certain amount of power will be drawn by the integrated circuit. This amount of power depends upon the types of operations the circuit is performing. For example, operations requiring large amounts of switching produce correspondingly large amounts of power dissipation.
Hence, the power dissipation experienced by the integrated circuit varies over time as the integrated circuit functions. During certain operations, the integrated circuit will experience peak power dissipation, where the amount of power dissipated by the circuit per unit of time is at maximum. Peak power affects the amount of heat generated by the integrated circuit. Hence, peak power typically equates to peak heat generation.
Heat generation is not uniformly spread across the area of the integrated circuit. Peak heat generation corresponds to peak power requirements, which in turn corresponds to circuit switching activity. For example, during certain operations some portions of the integrated circuit may be relatively inactive (e.g., memory elements) while other portions are highly active (e.g., arithmetic logic units). The non-uniform heat generation leads to the development of “hot spots” within the area of the integrated circuit die. The hot spots are the first areas of the integrated circuit to be adversely affected by higher levels of heat generation.
Thus, the existence and the characteristics of such hot spots are one of the primary limiting factors on the maximum potential operating speed of the integrated circuit. Accordingly, “peak power” is an important parameter that affects the life of circuit. Excessive localized heat generation leads to thermal breakdown of the actual integrated circuit elements themselves (e.g., electron migration, etc.).
In accordance with the prior art, circuit developers use EDA tools (e.g., netlist simulations, etc.) during the design phase in an attempt to predict the peak power dissipation of the device, and thereby design higher performance integrated circuit devices. For example, a netlist description of the device is loaded onto an EDA simulation tool for optimization in accordance with, for example, a set of power dissipation constraints. The simulation tool stimulates the netlist using a large series of test inputs in an attempt to stimulate its operation and predict therefrom the power requirements and characteristics of the device. The results of the simulation allow the device to be optimized with respect to peak power and peak heat generation. Increasing levels of integration unfortunately leads to increasing complexity of the simulation and a corresponding increase in the difficulty of the optimization process.
As described above, peak power in high-density integrated circuits has a great impact on power budgeting, packaging, as well as circuit's reliability. However, performance and reliability requirements continue to drive the design process towards ever greater levels of integration and ever greater operating speeds. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns (e.g., inputs to the netlist of integrated circuit) to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small number of primary inputs, it is computer time intensive to conduct exhaustive search of the input vector space.
Because of this large input vector space, the compiling and optimization of large integrated circuit designs typically require one, o
Jiang Yi-Min
Wang Chuan-Yu
Wang Ping-Hann Peter
Garbowski Leigh M.
Synopsys Inc.
Wagner , Murabito & Hao LLP
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