Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-09-24
2011-10-25
Wang, Albert (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C327S116000, C327S122000, C455S118000
Reexamination Certificate
active
08046621
ABSTRACT:
Aspects of a method and system for generation of signals up to extremely high frequency using a delay block are provided. In this regard, a first signal may be delayed, via at least a portion of a plurality of delay elements and via a variable capacitance, to generate a second signal that is 90° out of phase relative to the first signal. Additionally, the first signal and second signal may be mixed to generate a third signal, wherein a frequency of the third signal is twice a frequency of said first signal. The portion of the delay elements utilized for delaying the signal may be controlled via one or more switching elements. In this regard, one of the plurality of delay elements may be selected to output the second signal. Moreover, the portion of the delay elements utilized for delaying the signal may be programmably controlled.
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USPTO Office Action Mailed, Aug. 6, 2009 for U.S. Appl. No. 11/860,152, filed Sep. 24, 2007.
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Broadcom Corporation
McAndrews Held & Malloy Ltd.
Wang Albert
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