Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-16
2007-10-16
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10966993
ABSTRACT:
A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.
REFERENCES:
patent: 5295082 (1994-03-01), Chang et al.
patent: 5414637 (1995-05-01), Bertin et al.
patent: 5450022 (1995-09-01), New
patent: 5627999 (1997-05-01), Cheng et al.
patent: 5808901 (1998-09-01), Cheng et al.
patent: 5822214 (1998-10-01), Rostoker et al.
patent: 6099583 (2000-08-01), Nag
patent: 6137307 (2000-10-01), Iwanczuk et al.
patent: 6526563 (2003-02-01), Baxter
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6675361 (2004-01-01), Crafts
patent: 6941537 (2005-09-01), Jessep et al.
patent: 2002/0178429 (2002-11-01), Nakayama et al.
patent: 2005/0132317 (2005-06-01), Kolk et al.
patent: 2005/0138592 (2005-06-01), Morgan et al.
patent: 2006/0080631 (2006-04-01), Koo
Kar et al., “Optimizing C4 Bump Placements for a Peripheral I/O Design”, 1999 Proceedings of 49th Electronic Components and Technology Conference, Jun. 1, 1999, pp. 250-254.
Ezawa et al., “Eutectic Solder Bump Process for ULSI Flip Chip Technology”, Twenty-First IEEE/CPMT Electronics Manufacturing Technology Symposium, Oct. 13, 1997, pp. 293-298.
Alander et al., “Solder Bump Reliability-Issues on Bump Layout”, IEEE Transactions on Advanced Packaging, vol. 23, No. 4, Nov. 2000, pp. 715-720.
U.S. Appl. No. 10/618,404, filed Jul. 11, 2003, Young.
U.S. Appl. No. 10/683,944, filed Oct. 10, 2003, Young.
U.S. Appl. No. 10/966,554, filed Oct. 15, 2004, Roberts et al.
Cadence; “Virtuoso Layout Editor”; Datasheet; Copyright 2003; available from Cadence Design Systems, Inc.; Sep. 2003; pp. 1-4.
M. Taliercio et al.; “A Procedural Datapath Compiler for VLSI Full Custom Applications”; IEEE 1991 Custom Integrated Circuits Conference; pp. 22.5.1 to 22.5.4, 1991.
Roberts Mark B.
Roberts Scott K.
Hardaway Michael R.
Kanzaki Kim
Kik Phallaka
Xilinx , Inc.
LandOfFree
Method and system for generating implementation files from a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for generating implementation files from a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for generating implementation files from a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3865453