Method and system for generating clocks for standby mode...

Details Method and system for generating clocks for standby mode... Method and system for generating clocks for standby mode...

2004-09-01

2009-02-24

Suryawanshi, Suresh K (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C365S229000, C455S574000

Reexamination Certificate

active

07496774

ABSTRACT:
Reducing power while in standby mode may comprise monitoring for an occurrence of at least one event requiring a transition out of a standby mode while utilizing a lower frequency, less accurate, and low power standby clock signal while operating in the standby mode. After receiving the occurrence of the event, an identity of the received event may be determined. In response to receiving the event, based on the determined identity of the event, a first and/or a second clock signal may be enabled, which has higher frequency and better accuracy and consumes more power than the standby clock signal. If the first and/or second clock signal is enabled, they may be disabled in order to re-enter the standby mode, which utilizes the standby clock signal while in standby mode.

REFERENCES:
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patent: 7210054 (2007-04-01), Jahagirdar et al.
patent: 11167441 (1999-06-01), None

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