Method and system for generating a schematic representing...

Details Method and system for generating a schematic representing... Method and system for generating a schematic representing...

2005-04-05

2005-04-05

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06877140

ABSTRACT:
A method (300) of generating a simplified netlist using bus information includes the steps of identifying (302) nets that form buses in a netlist and identifying (304) instances of a same type that connect to the identified nets via pins of the same name to form at least one set of instances. The method further includes the step of replacing (308) at least one set of instances with at least a single arrayed instance if each net in a bus is connected to exactly one of the same type of instance via a pin of the same name and the step of deleting the nets forming the arrayed instance from the netlist and replacing (314) the nets with a corresponding bus.

REFERENCES:
patent: 5883807 (1999-03-01), Fanjoy
patent: 6493648 (2002-12-01), Anderson
patent: 6574787 (2003-06-01), Anderson
Stephen T. Frezza, Steven P. Levitan; “SPAR: A Schematic Place and Route System”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 7; Jul. 1993; pp. 956-973.

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