Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-07-28
2001-03-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C340S870030
Reexamination Certificate
active
06205574
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to field programmable gate arrays, and more particularly to methods and systems for generating programming bitstreams for field programmable gate arrays.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure because of the re-programmability of FPGAs. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
The re-programmability of FPGAs, while a chief advantage of FPGAs over other solutions, has also created challenges to users of FPGAs, as well as to field engineers and other support personnel. Specifically, to trace the content of a particular FPGA programming bitstream, a user may need to reference identifying characteristics of certain design modules that are not readily available. The reason for the need to ascertain these characteristics arises from the fact that the design modules that are embodied in the programming bitstream have associated therewith characteristics such as logic core identifiers, revision levels, timestamps and assorted other information, and the identification of these characteristics may be necessary in order to troubleshoot problems that may arise from use of a particular design module with a particular FPGA. However, quickly identifying the characteristics may be cumbersome and time consuming depending upon how such information is managed.
In addition to the content of an FPGA programming bitstream, the software tools used to generate the bitstream may also impact operability. For example, when support personnel are presented with a programming bitstream which does not program a FPGA to function as expected, one consideration is the compatibility of the software tool with the particular FPGA. In addition, there may be compatibility issues between different versions of the software tool and revision levels of FPGAs. As with identification of the contents of the programming bitstream, identifying the software tools may be cumbersome or impossible depending upon how such information is managed.
Therefore, a method and system that addresses the aforementioned problems, as well as other related problems, are desirable.
SUMMARY OF THE INVENTION
A method and apparatus for generating a programming bitstream for a programmable gate array are provided in various embodiments of the invention. Certain segments of a programming bitstream generated from an input design specification are unused for storing programming bits. Selected items of information are encoded and stored in the unused segments of the programming bitstream.
In a first embodiment, a method is provided for generating a programming bitstream for the programmable gate array in response to an input design specification. The programming bitstream includes one or more unused segments, wherein an unused segment includes bits that are not used for programming the programmable gate array. One or more selected items of information are encoded to form binary representations of the items. The binary representations are inserted into one or more of the unused segments of the programming bitstream.
In another embodiment, a method is provided for generating a programming bitstream for a programmable gate array and ascertaining identification information from the programming bitstream. One or more selected items of information are encoded to form binary representations of the items. The binary representations are inserted into one or more of the unused segments of the programming bitstream. Binary representations of the items of information are read from the unused segments and the binary representation are decoded into the selected items of information.
A method for ascertaining identification information from a programming bitstream for a programmable gate array is provided in yet another embodiment. One or more of the unused segments have encoded therein binary representations of one or more selected items of information. The method comprises reading from at least one of the unused segments of the programming bitstream binary representations of one or more selected items of information. The binary representations are decoded into the selected items of information.
In another embodiment, an apparatus for generating a programming bitstream for a programmable gate array comprises: means for generating a programming bitstream for the programmable gate array including one or more unused segments in response to an input design specification; means for encoding one or more selected items of information to form binary representations of the items; and means for inserting the binary representations into one or more of the unused segments of the programming bitstream.
A system for generating a programming bitstream for a programmable gate array is yet another embodiment of the invention. The system comprises a bitstream generator configured to generate a programming bitstream responsive to an input design specification. The programming bitstream has one or more unused segments that are not used for programming the programmable gate array. An information encoder is coupled to the bitstream generator and configured to encode one or more selected items of information into respective binary representations and insert the binary representations into one or more of the unused segments of the programming bitstream.
In yet another embodiment, identification bits are appended to the bitstream rather than inserted into unused bits. In this embodiment, the bitstream is lengthened in order to accommodate the identification bits. The process for generating the bitstream of this embodiment is simpler than that of inserting identification bits into an existing bitstream, since the improved bitstream can simply be formed by adding the identification bits to the end of an existing bitstream. The improved bitstream is usually compatible with an older bitstream even though the bitstream must be made longer to accommodate the added bits. Typically, a header at the beginning of the bitstream specifies the length of the bitstream. This header is revised to specify the added length. In the FPGA, the added identification bits are simply passed through the device and not used.
In a combination embodiment, some identification bits are embedded in the bitstream and additional bits are appended to the bitstream.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
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Dellinger Eric F.
Iwanczuk Roman
Kik Phallaka
Maunu LeRoy D.
Smith Matthew
Xilinx , Inc.
Young Edel M.
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