Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2001-07-16
2002-09-10
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S459000, C700S121000
Reexamination Certificate
active
06448152
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of manufacturing objects. More specifically, the present invention relates to the field of manufacturing semiconductor wafers.
BACKGROUND ART
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs. Some integrated circuits are fabricated on a slice or wafer, of single-crystal (monocrystalline) silicon, commonly termed a “bulk” silicon wafer. Devices on such “bulk” silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (LOCOS) process, trench isolation, and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip. Additionally, trench isolation often requires a process of reactive ion etching, which is extremely time consuming and can be difficult to achieve accurately.
An approach to achieving very-large scale integration (VLSI) or ultra-large scale integration (ULSI) is by using a silicon-on-insulator (SOI) wafer. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. A variety of techniques have been proposed or used for fabricating SOI wafers. These techniques include, among others, growing a thin layer of silicon on a sapphire substrate, bonding a layer of silicon to an insulating substrate, and forming an insulating layer beneath a silicon layer in a bulk silicon wafer. In an SOI integrated circuit, essentially complete device isolation is often achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. An advantage SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on SOI wafers may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. However, it should be appreciated that there are disadvantages associated with fabricating SOI wafers.
One of the disadvantages is that fabricating a batch of substantially uniform SOI wafers such that they satisfy a predefined set of parameters typically is a time consuming process. Therefore, if a customer (for example) orders a batch of SOI wafers that are to satisfy certain parameters, the turnaround time to fulfill the order generally has a negative affect on how quickly the particular product associated with the ordered SOI wafers is able to reach its market.
SUMMARY OF THE INVENTION
Accordingly, a need exists for a method and system which enables silicon-on-insulator (SOI) wafers to be fabricated more efficiently thereby reducing the turnaround time of fulfilling an order for a batch of predefined SOI wafers. The present invention provides a method and system which accomplishes the above mentioned need.
One embodiment of the present invention provides a method for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer. For example, a plurality of donor wafers with different silicon layer thicknesses along with a plurality of handle wafers with different oxide layer thicknesses are fabricated. Subsequently, a customer may place an order for silicon-on-insulator (SOI) wafers which share defined parameters. Therefore, a prefabricated donor wafer and handle wafer are selected based on the customer's defined parameters and then bonded together. Next, the donor wafer is cleaved from the handle wafer wherein the handle wafer retains the silicon layer of the donor wafer. The silicon layer thickness of the handle wafer may be altered to meet the customer's parameters. For example, an epitaxial smoothing process may decrease the silicon layer thickness while an epitaxial thickening process may increase the silicon layer thickness.
In another embodiment, the present invention includes a method for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer. The method includes the step of receiving a desired layer thickness. Furthermore, the method includes the step of selecting a donor wafer based upon the desired layer thickness from a plurality of donor wafers having different thicknesses of a first material layer. Additionally, the method includes the step of selecting a handle wafer based upon the desired layer thickness from a plurality of handle wafers having different thicknesses of a second material layer. The method also includes the step of bonding the donor wafer and the handle wafer together. Moreover, the method includes the step of modifying the thickness of the first material layer to attain the desired layer thickness.
In yet another embodiment, the present invention includes a computer readable medium having computer readable code embodied therein for causing a system to perform particular steps. Specifically, the computer readable medium causes the system to perform the steps described within the previous paragraph.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5714395 (1998-02-01), Bruel
patent: 6300218 (2001-10-01), Cohen et al.
patent: 6321134 (2001-11-01), Henley et al.
Henley Francois J.
Kang Sien G.
Malik Igor J.
Sarkar Asok Kumar
Sherry Michael
Silicon Genesis Corporation
Wagner , Murabito & Hao LLP
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