Method and system for formal verification of an electronic...

Details Method and system for formal verification of an electronic... Method and system for formal verification of an electronic...

2011-02-15

2011-02-15

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07890903

ABSTRACT:
A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.

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Y. Chang, K. Cheng, Induction-Based Gate-Level Verification of Multipliers, University of California, Santa Barbara, CA, 2001 IEEE.
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D. Stoffel, W. Kunz; Verification of Integer Multipliers on the Arithmetic Bit Level; Institute of Computer Science, University of Frankfurt; 2001 IEEE.
R.E. Bryant, Y. Chen; Verification of Arithmetic Circuits with Binary Moment Diagrams; Carnegie Mellon University, 32ndDesign Automation Conference, Jun. 1995.

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