Method and system for formal unidirectional bus verification...

Details Method and system for formal unidirectional bus verification... Method and system for formal unidirectional bus verification...

2007-12-04

2007-12-04

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11065601

ABSTRACT:
A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.

REFERENCES:
patent: 2005/0125754 (2005-06-01), Schubert et al.

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