Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Utility Patent
1997-08-29
2001-01-02
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Utility Patent
active
06170080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method and system for implementing a circuit design. More particularly, the invention relates to a method and system for implementing a circuit design by floorplanning the design at a high level of abstraction.
2. State of the Art
An application specific integrated circuit (ASIC) is typically produced by developing a behavioral description of the desired circuit functions, determining a list of instances or blocks of logic needed to implement the desired functions, arranging the blocks of logic into a floorplan that meets desired constraints, and physically laying out the floorplan on the integrated circuit.
Currently, most floorplanning tools work at a relatively low, level of abstraction using structural netlists. A conventional process used to implement a circuit design is illustrated in FIG.
1
a
. As shown in FIG.
1
a
, the designer inputs a Register Transfer Level circuit design into a synthesis tool at step
100
and, using estimated wire load models, produces a netlist file (e.g., {nls}file). At step
110
, the designer floorplans the netlist using a floorplanning tool. This produces a physical data electronic format file (e.g., {pdf}file) which includes a list of clusters (i.e., groups of instances representing functional blocks of logic), a wire load model file (e.g., {wlm}file) which includes the names of the wire load models of the physical clusters, and a floorplanning file (e.g., {flr}file) which holds the floorplan. The designer then re-synthesizes the circuit design at step
120
using the wire load models, the clustering information, the netlist file produced at step
100
, and timing and design rule constraint files (e.g., {tco}file and {dco}file). This re-synthesis produces a new netlist file (e.g., {nls}file′) listing of which instance belongs to which cluster. Finally, the designer re-floorplans the new netlist at step
130
, using the new netlist file and the floorplanning file created at step
110
.
There are many drawbacks to the conventional process shown in FIG.
1
a
. One drawback is that the designer synthesizes the circuit design twice. Another drawback is that the designer exchanges large data files between several Electronic Data Automation (EDA) tools many times. The FIG.
1
a
process also involves describing the circuit design using a hardware description language (HDL) before starting the floorplan of the circuit design. As such, this conventional process wastes time and resources.
There is thus a need for a system and method of circuit design and implementation by which a designer can floorplan a circuit design at a high level of abstraction. This need is because the circuit designer may want to begin to floorplan the design at a high level of abstraction before finishing the netlist. For example, the designer may want to estimate the physical size of circuit design or to place certain critical entities close together to speed the signal propagation time of these entities. Alternately, the designer may want to floorplan at a high level of abstraction so that inter-block wiring capacitances and intra-block wire load models can be estimated before the circuit design is completed. This information is important for good synthesis and optimization of the circuit design. As such, a netlist of the circuit design must be produced before a system designer working at a high level of abstraction, such as the Register Transfer Level (RTL), can floorplan the circuit design.
SUMMARY OF THE INVENTION
The present invention is thus directed to providing a floorplanning tool which can operate at a high level of abstraction. Exemplary embodiments are directed to a floorplanning tool which can read and represent an original logical hierarchy at a high level of abstraction, and which can perform block placement at a high level of abstraction. Further, exemplary embodiments permit the designer to manipulate logical entities in a circuit design without affecting other logical entities.
According to exemplary embodiments of the present invention, a floorplanning tool is provided by which a designer can break down a logical hierarchy to build a physical hierarchy or floorplan, thereby providing the designer information to help build the physical hierarchy. A floorplanning tool according to exemplary embodiments can also derive wire load models for the physical hierarchy, extract inter-block capacitance values and communicate them to a synthesis tool in order to drive the optimization process. Exemplary embodiments can communicate these wire load models, together with the physical hierarchy, to the synthesis tool to correctly drive it, and write a floorplanning file which includes the size and the location of the different areas.
Generally speaking, exemplary embodiments of the invention relate to a method and a system for implementing a circuit design in an integrated circuit by arranging a floorplan of the circuit design at a high level of abstraction. The circuit design is then synthesized based on the floorplan, and the synthesized design is laid out physically on an integrated circuit.
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Fernandes Jean-Michel
Ginetti Arnold
Giomi Jean-Charles
Silve Francois
Tarroux Gerrard
Burns Doane Swecker & Mathis L.L.P.
Garbowski Leigh Marie
Lintz Paul R.
VLSI Technology Inc.
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