Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-06-19
2004-04-20
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S052000, C710S039000, C710S009000, C710S010000, C711S003000, C711S109000, C711S219000, C711S220000, C711S110000, C711S170000, C711S202000
Reexamination Certificate
active
06725298
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and a system for filter-processing by ensuring a memory space for a ring-buffer.
As multi-media has been on the recent rapid growth, digital signal processors are frequently used for filter-processings in general with multiple functions. For example, a code excited linear prediction (CEL) processing as a voice compression processing is carried out by a prediction processing. For the purpose of the prediction processing, an encoder includes an algorithm of a decoder as a sub-set, for which reason a large number of filter-processings are commonly used. A plurality of size-different data tables are often referred in a single exclusive filter processing routine. As plural multimedia processings are performed on a real time operating system, it is necessary for efficiently using a limited memory resource to execute active operations of ensuring and releasing memory spaces during program operations.
The conventional filter processings will be described with reference to the drawing.
FIG. 1
is a block diagram illustrative of a configuration of a data addressing unit and a data memory space used in a digital signal processor.
FIG. 2
is a flow chart illustrative of a conventional operation of the filter processings. A data addressing unit
106
has a module register
108
, a data pointer register
107
and an arithmetic and logic unit
109
. The module register
108
is connected to a main bus
110
. The data pointer register
107
is also connected to the main bus
110
. The arithmetic and logic unit
109
is connected to the module register
108
and the data pointer register
107
. The data pointer register
107
is also connected to a data memory space
101
. The data memory space
101
has a ring-buffer
103
terminated with a top
104
and an end
105
. The data memory space
101
is also connected to a data bus
102
.
Operations of the filter processings will hereinafter be described with reference to FIG.
2
.
In a first step S
601
, an address for the top
104
of the ring buffer
103
as the object of the filter-process is set in the data pointer register
107
, wherein the address for the top
104
of the ring buffer
103
has low bits of zero in the bit number necessary for representing buffer size. In the prior art, the address of the top
104
of the ring-buffer
103
is not actively determined in the filter-processing. A fixed address is used which has been allocated by a designer for the filter-processing.
In a second step S
203
, a buffer size of the ring-buffer is set in the ring-buffer register
108
.
In a third step S
204
, a filter-processing is carried out by sequential accesses to the ring-buffers
103
. Even, during the filter-processing, a value of the data pointer register
107
for access to the ring-buffer
103
is subjected to an automatic adding operation for the address whereby the value of the data pointer register
107
is beyond the end
105
of the ring-buffer
103
, then an adjustment to the address is always made by the ring buffer register
108
and the arithmetic and logic unit
109
in the data addressing unit
106
without an adjustment to the address by software.
FIG. 3
is a flow chart illustrative of a conventional process for two filters.
FIG. 4
is a memory map illustrative of the conventional process for two filters of FIG.
3
.
In a first step S
701
, as a top address of a first ring-buffer “A”, a fixed address allocated by the filter designer is set.
In a second step S
403
, a buffer size of the first ring-buffer “A” is set in the ring buffer register.
In a third step S
702
, as a top address of a second ring-buffer “B”, another fixed address allocated by the filter designer is set.
In a fourth step S
406
, a buffer size of the second ring-buffer “B” is set in the ring buffer register.
In a fifth step S
407
, a filer
1
is processed. A ring-buffer “C” is not used for the filter
1
, and also parts
10
-
20
of the ring-buffer “A” are not used for the filter
1
. Notwithstanding, the ring-buffer “C” and the parts
10
-
20
of the ring-buffer “A” are ensured for processing the filter
1
. Accordingly, not only use memory spaces but also non-use memory spaces are ensured to correspond to the maximum value of the buffer. The non-use memory space is unavailable for the other processes than the process for the filter
1
.
In a third step S
703
, as a top address of a third ring-buffer “C”, another fixed address allocated by the filter designer is set.
In a fourth step S
412
, a buffer size of the third ring-buffer “C” is set in the ring buffer register.
In a fifth step S
413
, a filer
2
is processed. The ring-buffers “B” and “C” are not used for processing the filter
2
. Notwithstanding, the ring-buffers “B” and “C” are ensured for processing the filter
1
. Accordingly, not only use memory spaces but also non-use memory spaces are ensured to correspond to the maximum value of the buffer. The non-use memory space is unavailable for the other processes than the process for the filter
2
.
Consequently, the conventional method and system have the following problems.
The first problem is a low efficiency in use of the memory spaces. In order to execute the filter-process to the plural ring-buffers different in size from each other, the memory space is ensured corresponding to the maximum size. This memory space will remain ensured even after the filter-process. The memory space once ensured for the one filter process will be unavailable for any other processes.
The second problem is a complicated memory management. In view of the architecture of the digital signal processor, the low bit of the address for the top of the ring buffer is zero in the bit number necessary for representing buffer size. The calculation of those addresses is made by the filter-designer for every ring-buffers so as to place the ring-buffers at fixed ring-buffer addresses.
In the above circumstances, it had been required to develop a novel method and a system for filter-processing by ensuring a memory space for a ring-buffer free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel method for filter-processing by ensuring a memory space for a ring-buffer free from the above problems.
It is a further object of the present invention to provide a novel system for filter-processing by ensuring a memory space for a ring-buffer. The first present invention provides a method of processing at least a filter by ensuring a ring-buffer memory space in a digital signal processor, wherein if ring-buffer data stored in the ring-buffer memory space becomes no longer necessary after a filter-process is carried out, the ring-buffer memory space is released.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
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patent: 5787497 (1998-07-01), Tokura et al.
patent: 5913229 (1999-06-01), Joo
patent: 6044434 (2000-03-01), Oliver
patent: 6112267 (2000-08-01), McCormack et al.
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patent: 6404776 (2002-06-01), Voois et al.
patent: 0 784 287 (1997-07-01), None
patent: 0 837 561 (1998-04-01), None
Kenji Fujita, “In an Age in which DSP is more Competitive than CPU Performance,” Nikkei bytes, Nikkei BP Company, 1994, pp. 108-115.
M. Inoue, Digital Signal Processing Programming; Interface, CQ Publication Co., 1997, pp. 223-236.
Gaffin Jeffrey
NEC Electronics Corporation
Patel Niketa
Young & Thompson
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