Method and system for fault-tolerant static timing analysis

Details Method and system for fault-tolerant static timing analysis Method and system for fault-tolerant static timing analysis

2001-02-09

2004-09-21

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06795951

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to timing analysis of logic networks to determine whether the system will meet timing requirements for all possible combinations of inputs and internal states. The technique disclosed herein offers a new tool for circuit design by including in the timing analysis time delay shifts due to such factors as manufacturing abnormalities not serious enough to cause a hard failure, conductor coupling, or floating component elements in newer technologies such as SOI.
2. Description of the Related Art
Traditional static timing analysis methods, such as one based on the graph shown in
FIG. 1
, attempt to determine whether a logic network will meet a set of timing requirements for all possible combinations of input and state information. The timing is computed based on a smooth distribution of delays in the network and assumes that all these elements are operating as designed and are free from defects which would alter their delays. This presumption is not always realistic.
Presently, there is no adequate technique for analyzing delays due to such factors as low probability coupling between adjacent signal lines within a circuit, or due to manufacturing steps that are imperfect but not so serious as to cause an outright failure. Such manufacturing imperfections, or defects, may occur due to effects in newer technologies such as partially-depleted silicon-on-insulator (PD-SOI) where elements such as the bodies of transistors are floating rather than being electrically connected to any other node or the chip substrate. Changes in the voltage of such floating elements cause changes in threshold voltages, which in turn cause shifts in circuit delays. A class of defects is suspected of causing these floating elements to have higher leakage current, which can shift the balance of body currents and thereby shift the body voltage and the circuit delays. Newer technologies such as partially-depleted silicon-on-insulator (PD-SOI) have floating elements susceptible to such defects. This type of delay defect may have been present in older bulk technologies, but because such technologies did not have floating body elements, did not cause sufficient delay shifts to be noticeable. Thus, conventional static timing analysis techniques do not account for such circuit delay shifts except in very simplistic ways. Moreover, there has been no tool that can help a designer in such situations to isolate timing bottlenecks due to such delay shifts and make design decisions before circuit fabrication.
Delays in a logic network may not be exactly knowable, due to variations in the manufacture of the integrated circuit(s) in which the logic network is implemented, and due to various details of the design which, though theoretically predictable, are ignored (due to processing time limitations or inadequate modeling) in delay calculations. These variations tend to affect all delay edges in the network in a statistical manner. Many methods have been developed to account for such variations and/or the correlations between them, including Monte Carlo analysis, a method disclosed by Zaslo et al. in U.S. Pat. No. 4,924,430 which determines narrow distributions for the delays on a single chip from a wider distribution for the delays all instances of the chip, statistical summing of delays through propagation of mean and sigma ATs as was used in ETE, an early IBM static timing analyzer, the “linear combination of delays” (LCD) method, described by Dreibelbis et al. in an article titled “The Hidden Benefits of IBM ASICs: Part 1” which appeared in MicroNews, vol. 6, no. 3, published in 2000 by IBM Microelectronics, and used in EinsTimer, a static timing analyzer currently used by IBM, and the common-path pessimism removal (CPPR) method used in EinsTimer and described by Hathaway et al. in U.S. Pat. No. 5,636,372.
Defects in the circuit comprising a logic network can also cause variations in the delays of the network. In the past most defects which affected delays were likely to reduce the reliability of the network, and there was therefore no incentive to accommodate them in static timing analysis. Instead efforts were made to detect them in manufacturing test to avoid shipping unreliable parts. Examples of such faults are high resistance connections due to narrowed conductors or incompletely filled vias.
FIG. 2
shows a generalized distribution
20
of the types of circuit element delay variations accounted for by the conventional timing analysis techniques. The distribution for one delay edge is shown. Delay is shown along the horizontal axis, and the probability of the edge taking on a particular delay values is shown on the vertical axis. Conventional methods assume delays vary according to some smooth distribution, so a composite analysis can be a linear combination of delays using parameters such as propagation mean values and sigma ATs. Thus, conventional methods assume a delay distribution having a single peak.
With the introduction of partially-depleted of silicon-on-insulator (PD-SOI) technology it appears that there may be a class of defects which affects circuit delay but which does not otherwise affect the reliability or functioning of the circuit. This problem is not addressed by the above-described conventional technique. In PD-SOI devices the body of the transistor (the region in which the conductive channel forms) is typically floating (not electrically connected to any other node), unlike bulk technologies in which the device body is tied to the substrate (for NFETs) or to the Nwell (for PFETs). As a result, the body voltage will vary depending on the past history of the device, the exact value depending on the balance of source and drain junction diode currents, impact ionization current, and capacitive coupling. This body voltage variation causes a shift in the threshold voltage of the transistors, which in turn causes a variation in the circuit delays.
It appears that there may be a class of process defect which causes increased leakage of the source and drain diode junctions in a device. Such defects may have been present in past bulk technologies, but because the change in leakage caused is very small, and because the device bodies in these technologies were tied to ground (for NFETs) or Vdd (for PFETs), they would have had a negligible effect on device performance. In PD-SOI technologies, however, such increased leakage could shift the balance of body currents in a device, affecting the body voltage of the device and hence the delay of the circuit. Like other defects which induce delay variation, this is a very rare event and hence the probability that such a defect occurs more than once on any given path is negligible. However the probability that it would occur somewhere on a chip could be significant (there is speculation that perhaps one fourth of all chips exhibit such defects). Unlike other defects which induce delay variation, this appears to be a benign defect, in the sense that it does not worsen over the life of the chip, and hence does not affect the long term reliability of the chip.
A third type of time delay shift is one caused by coupling. As conductors on chips get closer together, the coupling between parallel sections becomes tighter. Typically, under normal operation this tighter coupling does not present a problem, but with ever tighter pitches between conductors, the chance becomes greater for significant shifts in time delay due to coupling between simultaneously transitioning conductors. Techniques are known in the art to compute the delay shift due to such coupling when it occurs, but because the exact alignment of transitions in adjacent conductors is rare, it is pessimistic to assume that all pairs of adjacent conductors always exhibit such a delay shift. The conventional techniques do not fully address the problems with infrequently occurring coupling delays.
FIG. 3
shows a distribution
30
of circuit element delay variations as modified to be a bimodal distribution having a prima

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