Method and system for fast data access using a memory array

Details Method and system for fast data access using a memory array Method and system for fast data access using a memory array

2007-11-27

2007-11-27

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

Reexamination Certificate

active

11598010

ABSTRACT:
First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

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European Search Report for European Application No. EP 02 25 4514, mailed Sep. 21, 2004, European Patent Office, The Hague.

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