Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Warping of semiconductor substrate
Reexamination Certificate
2006-08-22
2006-08-22
Pham, Hoai (Department: 2822)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Warping of semiconductor substrate
C438S455000
Reexamination Certificate
active
07094666
ABSTRACT:
A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(1) and is defined normal to the surface region. The method includes providing a first substrate (e.g., silicon wafer) having a first thickness. Preferably, the first substrate has a face, a backside, and a cleave plane defined within the first thickness. The method includes a step of overlying the backside of the first substrate on a portion of the surface region having the predetermined radius of curvature to cause a first bend within the thickness of material to form a first strain within a portion of the first thickness. The method provides a second substrate having a second thickness, which has a face and a backside. The method includes a step of overlying the face of the second substrate on a portion of the face of the first substrate to cause a second bend within the thickness of material to form a second strain within a portion of the second thickness. A step of joining the face of the second substrate to the face of the first substrate form a sandwich structure while maintaining the first bend in the first substrate and the second bend in the second substrate. Preferably, joining occurs using a low temperature process such as plasma activated bonding or the like.
REFERENCES:
patent: 3392069 (1968-07-01), Merkel et al.
patent: 4059428 (1977-11-01), Andrews
patent: 5374564 (1994-12-01), Bruel
patent: 5793913 (1998-08-01), Kovacic
patent: 5907770 (1999-05-01), Yamazaki et al.
patent: 6013563 (2000-01-01), Henley et al.
patent: 6020052 (2000-02-01), Johnson
patent: 6225192 (2001-05-01), Aspar et al.
patent: 6287941 (2001-09-01), Kang et al.
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6455397 (2002-09-01), Belford
patent: 6503773 (2003-01-01), Fitzgerald
patent: 6514836 (2003-02-01), Belford
patent: 6563152 (2003-05-01), Roberts et al.
patent: 6809009 (2004-10-01), Aspar et al.
patent: 6902616 (2005-06-01), Yamazaki et al.
patent: 2001/0039095 (2001-11-01), Marty
patent: 2002/0174828 (2002-11-01), Stefanescu et al.
patent: 2005/0020094 (2005-01-01), Forbes et al.
patent: 2005/0118754 (2005-06-01), Henley et al.
patent: 1085562 (2001-03-01), None
patent: WO 00/63965 (2000-10-01), None
patent: WO 01/54175 (2001-07-01), None
Ge et al, “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” IEDM (2003), 4 pages total.
Adam et al., SOI as a Mainstream IC Technology, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 9-12.
Belford et al., Performance-Augmented CMOS Using Back-end Uniaxial Strain, 2002 Devcie Research Conference, Santa Barbara, CA.
Comita et al., Low Temperature Si and SiGe Epitaxy for sub 01.pm Technology, AMAT Conference Paper, Mar. 10, 2003.
Chuang et al., Design Considerations of SOI Digital CMOS VLSI, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 5-8.
Feijo et al., Pre stressing of Bonded Wafers, Proceedings of the First International Symposium on Semiconductor Wafer Bonding Science, Technology and Applications (Electrochemical Society, New York, 1992, v. 92.7, pp. 230-238.
GE et al., Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering, IEEE International Electron Devices Meeting, Washington, DC, Dec. 2003.
Hobuka et al., Change in Micro roughness of a Silicon Surface during in Situ Cleaning Using HF and HCL Gases, Journal of the Electrochemical Society, Electrochemical Society, Manchester, NY, v. 145, No. 12, Dec. 1998, pp. 4264-4271.
Mantl et al., Enhanced Strain Relaxation of Epitomical SiGe-Layers ON Si (100) Improved by Hydrogen Implantation, Nuclear Instruments and Methods in Physics Research Section B, Jan. 1999, v. 147, Issue 1-4, p. 29-34.
Onjima et al., Lattice Relaxation Process of AIN Growth on Atomically Flat 6H-SIC Substrate in Molecular Beam Epitaxy, Journal of Crystal Growth, North-Holland Publishing Co., Amsterdam, NL, v. 2370239, Apr. 2002, pp. 1012-1016.
QE'S Smooth Approach Increases Carrier Mobilities, News, www.compoundsemiconductor.net, Dec. 2004.
Saenger, et al., Amorphization/templated recrystallization Method for Changing the Orientation of Single-Crystal Silicon: An Alternative Approach to Hybrid Orientation Substrates, Appl. Phys. Lett. 87.221911.2005.
Thomspson, Strained Silicon MOSFETs: The Next Material Change to Extend Moore's Law, University of Florida, Spring MRS 2004.
Yaguchi et al., Strain Relaxation in MBE-Grown SII-SGEX/SU(100) Heterostructures by Annealing, Japanese Journal of Applied Physics, Tokyo, JP, v. 30, No. 8B Part 2, Aug. 1991, pp. L1450-L1453.
Yang et al., On the Integration of CMOS with Hybrid Crystal Orientations, 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004.
Yang et al., High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations, IEDM Tech. Dig., 2003, pp. 453-456.
Henley Francois J.
Kirk Harry R.
Malik Igor J.
Ong Philip James
Duong Khanh
Pham Hoai
Silicon Genesis Corporation
Townsend & Townsend and Crew LLP
LandOfFree
Method and system for fabricating strained layers for the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for fabricating strained layers for the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for fabricating strained layers for the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3671651