Method and system for extracting high current parasitic bipolar

Details Method and system for extracting high current parasitic bipolar Method and system for extracting high current parasitic bipolar

1997-04-25

1999-09-07

Teska, Kevin J.

Boots, shoes, and leggings

364490, 257360, G06F 1750

Patent

active

059496940

ABSTRACT:
An embodiment of the instant invention is a method of optimizing an I/O circuit formed on a substrate with regards to an overvoltage or ESD event wherein the I/O circuit comprises at least one MOS device which has I-V characteristics, the method comprising the steps of: extracting selective electrical characteristics of the MOS device while the MOS device is operating in the avalanche and snapback regions of the I-V characteristics of the MOS device; characterizing the MOS device for the overvoltage or ESD event based on the electrical characteristics of the MOS device under standard operating conditions, the MOS device being comprised of a parasitic bipolar transistor and the substrate having a resistance; and wherein the I/O circuit is optimized for the overvoltage or ESD events by modifying the I/O circuit based on the electrical characteristics of the MOS device in conjunction with the characterization of the parasitic bipolar transistor and the substrate resistance.

REFERENCES:
patent: 5301084 (1994-04-01), Miller
patent: 5404041 (1995-04-01), Diaz et al.
patent: 5450267 (1995-09-01), Diaz et al.
patent: 5468667 (1995-11-01), Diaz et al.
patent: 5477414 (1995-12-01), Li et al.
patent: 5623387 (1997-04-01), Li et al.
patent: 5629545 (1997-05-01), Leach
patent: 5637892 (1997-06-01), Leach
patent: 5689133 (1997-11-01), Li et al.
patent: 5710689 (1998-01-01), Becerra et al.
patent: 5733794 (1998-03-01), Gilbert et al.
patent: 5744841 (1998-04-01), Gilbert et al.
Anerasekera et al., Modeling Mos Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations, Reliability Physics Symposium, 1996, 34th Annual Proceedings, IEEE, pp. 318-326.
Anerasekera et al., Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations, IEEE Circuits and Devices Magazine, Mar. 1997, vol. 132, pp. 7-10.
Chen et al., Design Methodology for Optimizing Gate Driven ESD Protection Circuits in Submicron CMOS Processes, Electrical Overstress/Electrostatic Discharge Symposium, 1997 Proceedings, pp. 230-239.
Chen et al., Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits, Reliability Physics Symposium, 1996, 34th Annual Prceedings, IEEE, pp. 227-232.
Amerasekera et al., Characterization and Modeling of Second Breakdown in NMOST's for the Extraction of ESD-Related Process and Design Parameters, IEEE Transactions on Electron Devices, vol. 38, No. 9, Sep. 1991, pp. 2161-2168.
Amerasekera et al., ESD Failure Modes: Characteristics, Mechanisms, and Process Influences, IEEE Transactions on Electron Devices, vol. 39, No. 2, Feb. 1992, pp. 430-436.
Chatterjee et al., Design and Simulation of a 4kV ESD Protection Circuit for a 0.8 .mu.m BiCMOS Process, Electron Devices Meeting, 1991, IEEE, pp. 35.5.1-35.5.4.
Duvvury et al., ESD: A Pervasive Reliability Concern for IC Technologies, Proceedings of the IEEE, vol. 81, No. 5, May 1993, pp. 690-702.
Amerasekera et al., Prediction of ESD Robustness in a Process Using 2-D Device Simulations, Reliability Physics, 1993 IEEE 31st Annual Proceedings, pp. 161-167.
Amerasekera et al., The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design, IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part A, vol. 18, No. 2, Jun. 1995,pp. 314-320.
Chen et al., Bipolar SCR ESD Protection Circuit for High Speed Submicron Bipolar/BiCMOS Circuits, IEEE Electron Devices Meeting, 1995 Technical Digest, pp. 337-340.
Voldman et al., Mixed-Voltage Interface ESD Protection Circuits for advanced Microprocessors in Shallow Trench and LOCOS Isolation CMOS Technologies, IEEE Electron Devices Meeting, 1994, pp. 277-280.

Affiliated with

Also associated with

Rating

Method and system for extracting high current parasitic bipolar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for extracting high current parasitic bipolar , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for extracting high current parasitic bipolar will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1810806