Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-06-28
2005-06-28
Anderson, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S117000, C711S119000, C711S122000, C711S130000, C711S143000, C711S145000
Reexamination Certificate
active
06912624
ABSTRACT:
To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.
REFERENCES:
patent: 5386547 (1995-01-01), Jouppi
patent: 5440752 (1995-08-01), Lentz et al.
patent: 5457679 (1995-10-01), Eng et al.
patent: 5634110 (1997-05-01), Laudon et al.
patent: 5778437 (1998-07-01), Baylor et al.
patent: 6167489 (2000-12-01), Bauman et al.
patent: 6202127 (2001-03-01), Dean et al.
patent: 6263405 (2001-07-01), Irie et al.
patent: 6295598 (2001-09-01), Bertoni et al.
patent: 6457100 (2002-09-01), Ignatowski et al.
patent: 6560681 (2003-05-01), Wilson et al.
patent: 6587931 (2003-07-01), Bauman et al.
patent: 6629209 (2003-09-01), Arimilli et al.
patent: 6701416 (2004-03-01), Arimilli et al.
patent: 6725334 (2004-04-01), Barroso et al.
Mukherjee, Shubhendu et al., “Using prediction to accelerate coherece protocols”, 1063-6897/98 (1998 IEEE).
Lee Joonwon et al., “Synchronization with Multiprocessor Cache”, CH2887-8/90/0000/0027 (1990 IEEE).
Agrawal, Anant, et al., “An Evaluation of Directory Schemes for Cache Coherence”, Proceedings of 15th International Symposium on Computer Architecture (“ISCA”) (May 1998) pp. 280-289.
Barroso, Luiz Andre, et al., “Impact of Chip-Level Integration on Performance of OLTP Workloads”, High-Performance Computer Architecture (“HPCA”) (Jan. 2000).
Barroso, Luiz Andre, et al., “Memory System Characterization of Commercial Workloads”, ISCA (Jun. 1998).
Eggers, Susan J., et al., “Simulation Multihreading: A Platform for Next-generation Processors”, University of Washington, DEC Western Research Laboratory ((eggers.levyjlo)@cs.washington.edu) ((emer.stamm)@vssad.enet.dec.com) pp. 1-15 (1997).
Eickemeyer, Richard J., et al., “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments”, ACM (1996) (0-89791-786-3) pp. 203-213.
Gupta, Anoop, et al., “Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes”, Standford University, Computer Systems Laboratory, pp 1-10 (1990).
Hammond, Lance, et al., “A Single-Chip Multiprocessor”, IEEE (Sep. 1997) (0018-9162).
Hammond, Lance, et al., “Data Speculation Support for a Chip Multiprocessor”, Stanford University, Computer Systems Laboratory (http://www.hydra.stanford.edu/), (Oct. 1998).
Jouppi, Norman P., et al., “Tradeoffs in Two-Level On-Chip Caching”, WRL Research Report 93/3, Western Research Laboratory (WRL-Techreports@decwri.dec.com) (Dec. 1993) pp. 1-31.
Krishnan, Venkata, et al., “Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor”, University of Illinois at Urbana-Champaign (http://iacoma.cs.uiuc.edu) (1998).
Kuskin, Jeffrey, et al., “The Stanford FLASH Multiprocessor”, Stanford Univeristy, Computer Systems Laboratory (Jun. 6, 1996).
Laudon, James, et al., “The SGI Origin: A ccNUMA Highly Scalable Server”, Silicon Graphics, Inc. (laudon@sgi.com) (Jun. 1997).
Lenoski, Daniel et al., “The Directory-Based Cache Coherence Protcol for the DASH Multiprocessor”, IEEE (1990) (CH2887-8) pp. 148-159.
Nayfeh, Basem A., et al., “Evaluation of Design Alternatives for a Multiprocessor Microprocessor”, ACM (1996) (0-89791-786-3) pp. 67-77.
Nowatzyk, Andreas G., et al., “S-Connect: from Networks of Workstations to Supercomputer Performance”, 22nd Annual International Symposium on Computer Architecture (“ISCA”) (Jun. 1995).
Nowatzyk, Andreas, et al., “Exploiting Parallelism in Cache Coherency Protocol Engines”, Sun Microsystems Computer Corporation (Aug. 1995).
Olukotun, Kunle, et al., “The Case of a Single-Chip Multiprocessor”, Proceedings Seventh International Symposium Architectual Support for Programming Languages and Operating Systems (“ASPLOS VII”) (Oct. 1996).
Steffan, J. Gregory, et al., “The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization”, HPCA-4 (Feb. 1998) pp. 1-12.
Tremblay, Marc, “MAJC-TM-5200 AVLIW Convergent MPSOC”, Sun Microsystems, Inc., Microprocessor Forum (1999).
Kunkel, Steven, et al., “System Optimization for OLTP Workloads, IEEE (1999) (0272-1732) pp. 56-64.
Diefendorff, Keith, “Power4 Focuses on Memory Bandwidth”, Microdesign Resources, Microprocessor Report vol. 13, No. 13, Oct. 6, 1999.
Hammond, Lance, et al., “The Stanford Hydra CMP”, Standford University, Computer Systems Laboratory (http://www-hydra.stanford.edu) (Mar. 2000), In EEE Micro, V.20 No. 2.
Barroso Luiz Andre
Gharachorloo Kourosh
Nowatzyk Andreas
Anderson Matthew
Li Zhuo H.
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