Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-06-19
2007-06-19
Peyton, Tammara (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S056000, C711S170000, C711S171000, C713S001000
Reexamination Certificate
active
10858776
ABSTRACT:
A method is disclosed for exchanging data between a central processing unit (CPU) and an input/output processor (IOP). The CPU and IOP may both be senders or receivers depending on whether data is flowing to or from the CPU. Where data is flowing to the CPU, the CPU is the receiver and the IOP is the sender. Where data is flowing from the CPU, the CPU is the sender and the IOP is the receiver. A sender evaluates the amount of empty buffers and, in a preferred embodiment, whether there is more data coming to determine whether to release partially full buffers in its buffer pool. Partially full buffers may be released based on any threshold as desired from a simple integer to a complex algorithm. The evaluation of whether to release partially full buffers is preferably implemented where a sender obtains at least one data packet for sending to a receiver and where a sender obtains an empty buffer from a receiver.
REFERENCES:
patent: 6070202 (2000-05-01), Minkoff et al.
patent: 7093097 (2006-08-01), Herr et al.
patent: 7143263 (2006-11-01), Anand et al.
Gregson Richard J.
Peyton Tammara
Unisys Corporation
Volpe and Koenig
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